# CMOS inverter: circular reasoning to understand it?

I am confused by a litte detail with CMOS inverter. Note that I am really a beginner in CMOS "theory". Here is the electrical circuit:

At "first view", I understand the principle. If $$\V_{in}\$$ is high ($$\V_{in}=V_{DD}\$$), then the PMOS will be open and the NMOS closed. Thus $$\V_{out}=0\$$.

Reciprocally, $$\V_{in}=0\$$ implies the PMOS closed and NMOS closed thus $$\V_{out}=V_{DD}\$$

## My question

I have trouble when I look at the details. Let us consider $$\V_{in}\$$ high for instance. A PMOS will be closed for $$\V_{GS} < V_{Tp}<0\$$ (threshold voltage), and $$\V_{GS} > V_{Tn}>0\$$ for NMOS.

But for this I must identify where are source and drain. To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.

But as I do not know $$\V_{out}\$$ how can I find them ? $$\V_{out}\$$ is what I try to find so I am not supposed to know it (else the reasoning is circular)...

Is there an implicit assumption that "by design", for CMOS circuit, any voltage in the circuit will verify $$\0 < V < V_{DD}\$$. Applying this to $$\V_{out}\$$ I can deduce source and drain for both transistors and solve my issue ?

Because "in principle", I could imagine some negative voltages and because of that identifying what is source and drain is not straightforward here.

• Use $<stuff>$ to make latex work properly. You drew the schematic so you label where source and drain need to be. There is a right way and a wrong way BTW. Commented Jan 9, 2021 at 15:55
• @Andyaka I used $tex$ but it didn't work. I will try with the \\$ Commented Jan 9, 2021 at 15:57
• But for this I must identify where are source and drain. To identify where is the source and the drain of a transistor, I must find which one has the highest voltage. No, to identify source and drain you must know whether you have a P or N channel device, and then source is the common terminal of the inverter that that device forms, so the two sources connected to GND and VDD, the two drains go to the output. Commented Jan 9, 2021 at 16:02
• There is no ambiguity, P channel source is VDD, N channel source is GND, gates are tied together for input and drains are tied together for output. Commented Jan 9, 2021 at 16:11
• Your transistor will have bulk connected to source making it asymmetrical. Commented Jan 9, 2021 at 16:44

## 1 Answer

To identify where is the source and the drain of a transistor, I must find which one has the highest voltage.

But as I do not know $$\V_{out}\$$ how can I find them ? $$\V_{out}\$$ is what I try to find so I am not supposed to know it?

You know that the output voltage will never be greater than $$\V_{DD}\$$ or less than $$\V_{SS}\$$.

Therefore, for the PMOS device on the high side, the source is always the terminal connected to $$\V_{DD}\$$ and for the NMOS device on the low side, the source is the terminal connected to $$\V_{SS}\$$.

As others have pointed out in comments, if you're building this from three-terminal discrete MOSFETs you must properly connect the terminals designated by the manufacturer as the source and drain correctly or the body diode will conduct, and the FET will not be able to block current. If you're building the device within an IC, then you'll be able to connect the bulk terminal to the correct voltage rail, and the device will behave symmetrically, provided you don't try to drive either source or drain terminal beyond the rails.

• Thank you for the answer. Ok so the source and drain are provided by the manufacturer. The device not being symmetrical because the bulk is connected to the source (as explained by Andyaka in the comments). And "in general", the source of a PMOS must be connected to a voltage higher (or equal) than the drain. The source of an NMOS mst be connected to a voltage lower (or equal) than the drain. Would you agree with my statement ? Commented Jan 9, 2021 at 16:44
• @StarBucK, yes, that's correct. Commented Jan 9, 2021 at 16:47