I am using dspic33E series microcontroller. The most using peripheral is ADC. So, I go through the ADC Reference manual for dspic33E family microcontrollers from Microchip. In the FRM, they said that, this controller has 4 ADC channels, 16 ADC buffers for storing the converted ADC results each of 16 bit size. There are some configuration registers which should be correctly configured in order to use ADC accurately in time-critical applications. One main bit is SMPI<4:0> bit in the ADCxCON2 register. This bit<4:0> determines how many samples need to be generated per single ADC interrupt.This samples will be read from ADC buffers after interrupt is genenrated.
Total number of ADC buffers are 16. If I set the value in that 5 bit sized SMPI as 7, I will get 8 samples per interrupt of ADC and each sample is stored in each adc buffer after ADC conversion done. I will get those 8 converted values from ADC buffers,after interrupt is generated. So theoretically, maximum I can get 16 samples per ADC interrupt.
But, in datasheet, the 5 bit sized SMPI section has an option to set the sample count up to 32. But only 16 results can be stored in ADC buffer since that is the maximum count of ADC buffer in the peripheral.
I have searched in FRM to know the reason for setting SMPI value to 32 samples/interrupt, but couldn't find it.
I am not using DMA feature for ADC. I am only using ADC peripheral. Since the maximum capacity is only for 16 conversion results, why the SMPI bit is allowed to get 32 samples per interrupt. How those all 32 values are stored in 16 buffers?
Link for ADC FRM: https://ww1.microchip.com/downloads/en/DeviceDoc/70621c.pdf
Image 1: ADC Buffer peripheral image
Image 2: SMPI bit value selection ranges.