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Currently I am using the internal BlockRAM from a FPGA to safe the samples I am getting from an ADC with a frequency of 200MHz. In the future, I want to use equivalent time sampling to get a virtual resolution of around 500ps.

The BlockRAM has a size of a few MB. I want to safe around 2GB of ADC samples. I am considering using a DDR3/DDR4 RAM module that is typically used in PCs. I never saw someone using a PC RAM module to store data coming from an ADC.

Is it even possible to store the samples in a DDR3/DDR4 RAM module?

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    \$\begingroup\$ Does your FPGA have a DDR3/DDR4 memory controller? If so, then yes it is possible. Lots of commercial ADC boards use normal DDR SO-DIMMs. \$\endgroup\$
    – user1850479
    Jan 12, 2021 at 15:48
  • \$\begingroup\$ @user1850479 ok thanks alot. I will look for a FPGA with this kind of memory controller \$\endgroup\$
    – Yoomo
    Jan 12, 2021 at 15:51
  • \$\begingroup\$ @user1850479 I only found ADC boards that use SRAM. But SRAM is really expensive. What is the benefit of using SRAM instead of DDR3/4 RAM? \$\endgroup\$
    – Yoomo
    Jan 12, 2021 at 15:54
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    \$\begingroup\$ No refresh required for sram vs any dram (ddr or not), this is not insurmountable. \$\endgroup\$
    – crasic
    Jan 12, 2021 at 15:56
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    \$\begingroup\$ Not to be confused with SDRAM, which is just DRAM \$\endgroup\$
    – crasic
    Jan 12, 2021 at 15:59

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DRAM (including DDR) requires the use of a memory controller, which takes care of the low-level details of timing, protocol and refresh management. The FPGA platform you're using likely includes configurable IP for this.

Your life will be easier if you use AXI or AXI-S internally to move your data, as these will be supported by blocks such as DMA and routing, as well as the memory controller you ultimately settle on. (Does not apply if you use Lattice, who, last I checked, only supported Wishbone.)

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