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I work on analog amplifier and filter chain for an internal STM32H753VI 16bits ADC. The signal chain is based on ultra-low noise opamp LT6237 and differential driver LT1994. The sample-rate of ADC will be 96 kHz. I cascade opamp to create amplifier stage and sallen & key cells trying to minimize noise spectral density and keep output signal offset very low (I don't have power consumption limit here.) I try my best but I got problem with Low-pass frequency response, I don't know if my output can be connected directly to the ADC and I wonder if I do big mistake and how I can optimize the noise spectral density.

SCHEMATIC & FREQUENCY RESPONSE
schematic

1. LOW-PASS PROBLEM : WHY THIS STRANGE BEHAVIOR ?
The response of the whole chain got a strange behavior @1MH it come from the sallen & key low-pass filter. I don't where the increase of gain came at 1 MHz and I don't know how to correct this.

Can you help me to solve this problem ?

strange response

2. ADC ELECTRICAL COMPATIBILITY : CAN I CONNECT MY ADC "AS IS" ?
I don't know if I can connect directly STM32H753VI 16bits ADC to OUT+, OUT- and GND(AVSS). I just put antialias filter a 37kHz but I don't know if ADC and LT1994 impedance are compatible.

Can you help me to adjust my output to the ADC input ?

Here are the electrical caracteristics of the ADC
ADC caracteristics 1
ADC caracteristics 2
ADC caracteristics 3

3. LOOK LIKE "NOT TOO BAD" SIGNAL CHAIN OR NOT ?
Do you see big mistake or misconception at first view on my chain ?
Do I miss basic rules in analog chain design ?

4. NOISE SPECTRAL DENSITY OPTIMIZATION : CAN I OPTIMIZE ?
I try my best to achieve lower noise density but I am not very good in analog world.
Do you think it's possible to lower the noise density ?

In other word, do you think I can build this analog signal chain (notwithstanding opamp power supply decoupling capacitor, LDO and ultra-low noise voltage reference chip, etc..) with average chance of working ?

Thanks in advance for your help to understand what I do, but analog world is not simple and with time I lost all what I learn...

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2 Answers 2

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The response of the whole chain got a strange behavior @1MH it come from the sallen & key low-pass filter. I don't where the increase of gain came at 1 MHz and I don't know how to correct this.

I would step back and consider if that elaborate cascaded filter system even makes sense. You have an ADC with a 3.6 MHz sampling rate and target bandwidth of 37 KHz. Since you are oversampled by a factor of 100, the passive RC filter you put on the input to the ADC chip will give you 44 dB of alias rejection before you have even put a single opamp in circuit. You can then use a digital low pass filter and decimate to 96 kHz, or since it looks (if I understand correctly) like your MCU has hardware to do this automatically, use what it provides.

Do you actually need more alias rejection than that? My guess is no, but a second order filter would give you more alias rejection than the dynamic range of the ADC.

  1. NOISE SPECTRAL DENSITY OPTIMIZATION : CAN I OPTIMIZE ?

The ADC you're using only specs 83 dB SNR (13.5 bits), so I don't know that a lot of analog optimization is going to make a big difference here. Assuming you don't completely screw up the analog front end, you are probably going to be limited by the noise on the ADC.

One thing you can try since you only need a small bandwidth is oversample like discussed above. When you oversample, your SNR goes up with 0.5*log2(ratio), and you're oversampling by a ratio of 100, so you could gain about 3.3 additional bits of resolution. I would look into this.

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  • \$\begingroup\$ You enlighten me a lot with pointing out the hardware oversampling capacity of the STM32...I'm focus on analog to unload the MCU but oversampling (sum) and right bit shifting (divide) are donne in hardware. This simplify a lot my analog chain (I can remove the active low-pass filter) and increase my SNR... Many thank to pointing out this and twist my brain for better solution. \$\endgroup\$
    – rom1nux
    Jan 13, 2021 at 12:27
  • \$\begingroup\$ @rom1nux Great. One other question, you have Vocm set to Vref, but should that actually be Vref/2? Maybe I am misunderstanding the datasheet. \$\endgroup\$
    – user1850479
    Jan 13, 2021 at 14:23
  • \$\begingroup\$ yes, In this stage I want to go from single ended zero centered ("AC coupled" is the good word ?) to differential ended centered to VREF/2 ("DC coupled" if it's the good word). Do you think I just need to put a capacitor to ground on Vocm (and remove the "VREF" source on my schematic) ? \$\endgroup\$
    – rom1nux
    Jan 13, 2021 at 15:23
  • \$\begingroup\$ @rom1nux You need to provide Vref/2. The schematic shows Vref/1, which would saturate the ADC, so make sure that voltage is correct. I didn't check the datasheet, but I would put a decoupling capacitor on Vref/2 to make sure it is very stable. \$\endgroup\$
    – user1850479
    Jan 13, 2021 at 15:42
  • \$\begingroup\$ Ha ok, it's bad naming. effectively ST name fullscale reference VREF+/VREF- (VREF- is internally connected to AGND) and in my 20 year old scool lesson the center reference point is named VREF. You are right I will put 3V low noise reference voltage to VREF+ of the ADC and I will put VREF+/2 to Vocm. \$\endgroup\$
    – rom1nux
    Jan 13, 2021 at 16:14
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Scale all R x100 and C down /100 and don’t exceed OA current.

Define filter passband gain, ripple BW -3dB and bandstop f @ Nyquist rate sample/2 to be at least -50dB depending on worst case input SNR or noise voltage at this f to prevent aliasing noise on ADC.

I suggest f-3dB <= 1/4 to 1/3 sample rate depending SNR and stop attenuation needed.

The biggest problem is no specs.!

enter image description here

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  • \$\begingroup\$ Arf yes, I completely put aside the currents analysis I was obsessed by lowering the noise. I deserve a pair of slaps. I will check... Just to understand, you post your schematic to highlight the current flow in cascaded opamp.I don't understand the color meaning and chere the 39.82 mA flow ? And yes, you're right Tony, my spec are not explicitly written. I will add. Many thanks to take time to help me. \$\endgroup\$
    – rom1nux
    Jan 13, 2021 at 12:43
  • \$\begingroup\$ Scale my R.C Values as well, this is a Chebychev 30kHz \$\endgroup\$
    – Tony Stewart EE75
    Jan 13, 2021 at 13:00
  • \$\begingroup\$ I increase Rx10 and C/10 on the active filter and I reduce current through all stages without increasing the noise density, and know I'm in the opamp spec. Yip Ha ! (I try Rx100 & C/100 but this made opamp into oscillating). I could not increase x10 or x100 R1&R2 of the first stage high gain amplifier because this increase the noise density quickly. R2 is noise density dominant over the whole chain... \$\endgroup\$
    – rom1nux
    Jan 13, 2021 at 16:17
  • \$\begingroup\$ Spectral BW shape and noise density gain are separate issues than need LNA front end with modest gain then 2nd stage again, then filter \$\endgroup\$
    – Tony Stewart EE75
    Jan 13, 2021 at 17:21

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