0
\$\begingroup\$

I designed a pcb for GSM module, using all the specifications given by the manufacturer, to have a controlled impedance. But there is a small detail that escapes me and that is not documented. When the trace of the antenna arrives at the SMA connector, should the ground plane be opened or should I continue to keep a distance as for the whole trace? Some manufacturers, with the same module, open the ground plane to the maximum, others keep it constant.

What is the correct solution? enter image description here

I add a photo to explain better.

Thank you all and sorry for my english

\$\endgroup\$
  • \$\begingroup\$ welcome here! Your English is excellent, don't worry! \$\endgroup\$ – Marcus Müller Jan 13 at 19:52
  • \$\begingroup\$ Is the connector mounted on the top side or the bottom side? And do you have any freedom to change it? What frequency band are your signals? \$\endgroup\$ – The Photon Jan 13 at 19:56
  • \$\begingroup\$ In picture 1, there will definitely be an impedance change as the trace enters the area under the connector where the ground plane is cut back. How much of a problem that will be at the highest GSM frequency (1.9 GHz, I think), I can't say. \$\endgroup\$ – SteveSh Jan 13 at 20:13
  • \$\begingroup\$ Also, what's on the next layer down (into the page) under the trace and the connector region. \$\endgroup\$ – SteveSh Jan 13 at 20:15
  • \$\begingroup\$ And on figure 2, I would have thought they would place the via stitching right next to the trace on the GND plane, not pulled back like it's shown. \$\endgroup\$ – SteveSh Jan 13 at 20:16
0
\$\begingroup\$

For 1.5GHz with a 1/4Wave ~ 3cm and the SMT radius about 10% of this , it is unlikely to make a difference at this frequency so filling it will reduce ingress at shorter wavelengths, yet one wants to avoid solder bridges under the holes. In the end, it doesn't make a huge difference for GSM but would for higher frequencies. Only test validation will know for sure.

Background info

Track impedance \$Z_O=\sqrt{\dfrac{L}{C}}\$ and this depends on conductor/dielectric ratios for L/G and L/H or L/H/G ratios.

Coplanar gaps have less effect on C than dielectric gaps between trace and ground plane underneath.

I see no reason for Figure 1 as that raises the impedance up to 50% with a large increase in W/G. Although I do see a reason for preventing a solder bridge.

Guarded trace W/G=5/1 Coplanar Gap = 20% of Width

This is only for FR4.

Under SMT W/G = 0.20 or a 1-side only change in gap, this amounts to an increase of 4/0.2 or 20:1 with a possible rise of 50% in impedance.

enter image description here

I might consider a compromise but the Height of dielectric and effective Dk of PCB are unknown and may be different in each example you saw. Yet it's the ratios that matter in discontinuities for relative changes.

enter image description here

These differences will be manifested by S parameters on the harmonics of the signals or interference well above GSM band.

\$\endgroup\$
  • \$\begingroup\$ Thank you for your answer, i will try with two different prototypes. Thank you again for your time. \$\endgroup\$ – ikt Jan 15 at 18:35
  • \$\begingroup\$ It depends on your expected performance above the GSM band. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jan 15 at 21:20

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.