I am trying to initiate a MM2S stream read from the programmable logic of a Zynq board. I have inserted the AXI DMA IP, and intend to use the AXI-Lite interface on it to program the registers in the Programming Sequence from p70 of the user manual
However, Vivado seems to be automatically connecting the AXI-Lite interface on the DMA to the ps7_0_axi_periph (AXI Interconnect), as shown in the read-only automically generated verilog file below. It remains this way even after I reset the output products with the connection absent in the block design.
Basically I just want to use the AXI-Lite interface from inside the sandbox with my own signals to write to the registers that would be required to read data into the sandbox, but Vivado is not letting me disconnect the AXI interconnect from the DMA.
Am I doing something wrong?
Turns out a had a misconception. The AXI DMA Master looks like it is automatically an ARM/CPU master, and Vivado doesn't let me change it (see image). How can I connect a PL-based master to the DMA IP to read data into BRAM?