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I am trying to initiate a MM2S stream read from the programmable logic of a Zynq board. I have inserted the AXI DMA IP, and intend to use the AXI-Lite interface on it to program the registers in the Programming Sequence from p70 of the user manual

However, Vivado seems to be automatically connecting the AXI-Lite interface on the DMA to the ps7_0_axi_periph (AXI Interconnect), as shown in the read-only automically generated verilog file below. It remains this way even after I reset the output products with the connection absent in the block design.

Basically I just want to use the AXI-Lite interface from inside the sandbox with my own signals to write to the registers that would be required to read data into the sandbox, but Vivado is not letting me disconnect the AXI interconnect from the DMA.

Am I doing something wrong?


Update

Turns out a had a misconception. The AXI DMA Master looks like it is automatically an ARM/CPU master, and Vivado doesn't let me change it (see image). How can I connect a PL-based master to the DMA IP to read data into BRAM?


DMA AXI Lite Master is Automatically from Processing System

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  • \$\begingroup\$ I just want to use the AXI-Lite interface from inside the sandbox with my own signals to write to the registers that would be required to read data into the sandbox - not clear what you are trying to do. After resetting OP you should re-generate them. You do not need SG mode to read from DDR. \$\endgroup\$
    – Nazar
    Jan 13 at 20:30
  • \$\begingroup\$ @Nazar I can't regenerate them (Vivado gives error). Ultimately I am trying to use the AXI DMA IP from the programmable logic to get data from DDR. The user manual I linked (page 70) says I can program a sequence of registers to do so. I think I am supposed to write to them over AXI DMA IP's S_AXI_LITE port, but I was having issues connecting to it. Is this the standard way to fetch data over DMA from DDR? \$\endgroup\$
    – Jake Daly
    Jan 13 at 22:06
  • \$\begingroup\$ You can not regenerate, because the connections are not valid. The axi_lite is used to configure the DMA. You should allow connecting axi_lite through the axi_inteconnect to the ZYNQ/Microblaze. Once the DMA is properly connected to the microcontroller and mapped in memory, you need to run design validation to see if any errors. Only then you will be able to generate output products and proceed with synthesis \$\endgroup\$
    – Nazar
    Jan 14 at 15:14
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After speaking with an AE, I learned some useful information. The standard way of controlling the AXI-Lite interface on the DMA IP is via the CPU's master interface. It is possible however to use a different (even custom) master interface in the programmable logic, in which case the "Master Interface: /processing_system7_0/M_AXI_GP0" field in the Run Connection Automation window would not be 'greyed out'.

To create an IP that Vivado will be able to automatically associate with this interface (such that I can choose it from the drop down field and control the DMA with it), you need to go to Tools > Create and Package New IP > Create a new AXI4 Peripheral.

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