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I don't know muach about verilog, but i started to study it lately. So if these codes doesn't make sense at all, forgive me :D

I am writing a verilog code for Sinus lookup table.

for instance,

'd1 <= 16'b0000000000010001;
'd2 <= 16'b0000000000100011;
'd3 <= 16'b0000000000110101;  

'd1 is decimal value 1 and 16 bit equivalent value of it * 2^8 in binary. and so on...

I think I couldn't provide the relation between counter and decimal values.

Here comes my codes...

module TopModule(clk, count ,reset);

input reset;
output reg [3:0]count;
input clk;

always@(posedge clk)begin 

if(reset)
count=1;

else begin 

for(count=1; count=90; count=count+1) begin 
    
'd1 <= 16'b0000000000010001;
'd2 <= 16'b0000000000100011;
'd3 <= 16'b0000000000110101;
'd4 <= 16'b0000000001000111;
'd5 <= 16'b0000000001011001;
'd6 <= 16'b0000000001101011;
'd7 <= 16'b0000000001111100;
'd8 <= 16'b0000000010001110;
'd9 <= 16'b0000000010100000;
'd10 <= 16'b0000000010110001;
'd11 <= 16'b0000000011000011;
'd12 <= 16'b0000000011010100;
'd13 <= 16'b0000000011100110;
'd14 <= 16'b0000000011110111;
'd15 <= 16'b0000000100001001;
'd16 <= 16'b0000000100011010;
'd17 <= 16'b0000000100101011;
'd18 <= 16'b0000000100111100;
'd19 <= 16'b0000000101001101;
'd20 <= 16'b0000000101011110;
'd21 <= 16'b0000000101101110;
'd22 <= 16'b0000000101111111;
'd23 <= 16'b0000000110010000;
'd24 <= 16'b0000000110100000;
'd25 <= 16'b0000000110110000;
'd26 <= 16'b0000000111000000;
'd27 <= 16'b0000000111010000;
'd28 <= 16'b0000000111100000;
'd29 <= 16'b0000000111110000;
'd30 <= 16'b0000000111111111;
'd31 <= 16'b0000001000001111;
'd32 <= 16'b0000001000011110;
'd33 <= 16'b0000001000101101;
'd34 <= 16'b0000001000111100;
'd35 <= 16'b0000001001001011;
'd36 <= 16'b0000001001011001;
'd37 <= 16'b0000001001101000;
'd38 <= 16'b0000001001110110;
'd39 <= 16'b0000001010000100;
'd40 <= 16'b0000001010010010;
'd41 <= 16'b0000001010011111;
'd42 <= 16'b0000001010101101;
'd43 <= 16'b0000001010111010;
'd44 <= 16'b0000001011000111;
'd45 <= 16'b0000001011010100;
'd46 <= 16'b0000001011100000;
'd47 <= 16'b0000001011101100;
'd48 <= 16'b0000001011111000;
'd49 <= 16'b0000001100000100;
'd50 <= 16'b0000001100010000;
'd51 <= 16'b0000001100011011;
'd52 <= 16'b0000001100100110;
'd53 <= 16'b0000001100110001;
'd54 <= 16'b0000001100111100;
'd55 <= 16'b0000001101000110;
'd56 <= 16'b0000001101010000;
'd57 <= 16'b0000001101011010;
'd58 <= 16'b0000001101100100;
'd59 <= 16'b0000001101101101;
'd60 <= 16'b0000001101110110;
'd61 <= 16'b0000001101111111;
'd62 <= 16'b0000001110001000;
'd63 <= 16'b0000001110010000;
'd64 <= 16'b0000001110011000;
'd65 <= 16'b0000001110100000;
'd66 <= 16'b0000001110100111;
'd67 <= 16'b0000001110101110;
'd68 <= 16'b0000001110110101;
'd69 <= 16'b0000001110111011;
'd70 <= 16'b0000001111000010;
'd71 <= 16'b0000001111001000;
'd72 <= 16'b0000001111001101;
'd73 <= 16'b0000001111010011;
'd74 <= 16'b0000001111011000;
'd75 <= 16'b0000001111011101;
'd76 <= 16'b0000001111100001;
'd77 <= 16'b0000001111100101;
'd78 <= 16'b0000001111101001;
'd79 <= 16'b0000001111101101;
'd80 <= 16'b0000001111110000;
'd81 <= 16'b0000001111110011;
'd82 <= 16'b0000001111110110;
'd83 <= 16'b0000001111111000;
'd84 <= 16'b0000001111111010;
'd85 <= 16'b0000001111111100;
'd86 <= 16'b0000001111111101;
'd87 <= 16'b0000001111111110;
'd88 <= 16'b0000001111111111;
'd89 <= 16'b0000001111111111;
'd90 <= 16'b0000010000000000;

end 
end
endmodule

And this is my testbench

 module TestBench();

reg clk,reset;
wire count;

uut uut(.clk(clk),.reset(reset), .count(count));

initial begin
clk=0;
forever #10 clk=~clk;
end

initial begin
reset=0;
#1810;
reset=1;
end

endmodule
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3
  • \$\begingroup\$ What do you expect as the output? \$\endgroup\$ – dave_59 Jan 14 at 7:12
  • \$\begingroup\$ I wanna see binary values in order at the simulation \$\endgroup\$ – Abdulkadir Arslan Jan 14 at 7:19
  • \$\begingroup\$ Please ask a specific question. \$\endgroup\$ – Voltage Spike Jan 29 at 19:31
1
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Okay i figured out the solution.

Here are top module and testbench for these code.

`timescale 1ns / 1ps


module TopModule(clk, aci ,reset,sonuc,en);

input en;
input reset;
input [7:0]aci;
output reg [15:0]sonuc;
input clk;



always@(posedge clk)begin 

if(reset)
    sonuc <= 'd0;

else begin 
        
        case(aci)
        
            'd1 : sonuc <= 16'b0000001111111111;
            'd2 : sonuc <= 16'b0000001111111111;
            'd3 : sonuc <= 16'b0000001111111110;
            'd4 : sonuc <= 16'b0000001111111101;
            'd5 : sonuc <= 16'b0000001111111100;
            'd6 : sonuc <= 16'b0000001111111010;
            'd7 : sonuc <= 16'b0000001111111000;
            'd8 : sonuc <= 16'b0000001111110110;
            'd9 : sonuc <= 16'b0000001111110011;
            'd10 : sonuc <= 16'b0000001111110000;
            'd11 : sonuc <= 16'b0000001111101101;
            'd12 : sonuc <= 16'b0000001111101001;
            'd13 : sonuc <= 16'b0000001111100101;
            'd14 : sonuc <= 16'b0000001111100001;
            'd15 : sonuc <= 16'b0000001111011101;
            'd16 : sonuc <= 16'b0000001111011000;
            'd17 : sonuc <= 16'b0000001111010011;
            'd18 : sonuc <= 16'b0000001111001101;
            'd19 : sonuc <= 16'b0000001111001000;
            'd20 : sonuc <= 16'b0000001111000010;
            'd21 : sonuc <= 16'b0000001110111011;
            'd22 : sonuc <= 16'b0000001110110101;
            'd23 : sonuc <= 16'b0000001110101110;
            'd24 : sonuc <= 16'b0000001110100111;
            'd25 : sonuc <= 16'b0000001110100000;
            'd26 : sonuc <= 16'b0000001110011000;
            'd27 : sonuc <= 16'b0000001110010000;
            'd28 : sonuc <= 16'b0000001110001000;
            'd29 : sonuc <= 16'b0000001101111111;
            'd30 : sonuc <= 16'b0000001101110110;
            'd31 : sonuc <= 16'b0000001101101101;
            'd32 : sonuc <= 16'b0000001101100100;
            'd33 : sonuc <= 16'b0000001101011010;
            'd34 : sonuc <= 16'b0000001101010000;
            'd35 : sonuc <= 16'b0000001101000110;
            'd36 : sonuc <= 16'b0000001100111100;
            'd37 : sonuc <= 16'b0000001100110001;
            'd38 : sonuc <= 16'b0000001100100110;
            'd39 : sonuc <= 16'b0000001100011011;
            'd40 : sonuc <= 16'b0000001100010000;
            'd41 : sonuc <= 16'b0000001100000100;
            'd42 : sonuc <= 16'b0000001011111000;
            'd43 : sonuc <= 16'b0000001011101100;
            'd44 : sonuc <= 16'b0000001011100000;
            'd45 : sonuc <= 16'b0000001011010100;
            'd46 : sonuc <= 16'b0000001011000111;
            'd47 : sonuc <= 16'b0000001010111010;
            'd48 : sonuc <= 16'b0000001010101101;
            'd49 : sonuc <= 16'b0000001010011111;
            'd50 : sonuc <= 16'b0000001010010010;
            'd51 : sonuc <= 16'b0000001010000100;
            'd52 : sonuc <= 16'b0000001001110110;
            'd53 : sonuc <= 16'b0000001001101000;
            'd54 : sonuc <= 16'b0000001001011001;
            'd55 : sonuc <= 16'b0000001001001011;
            'd56 : sonuc <= 16'b0000001000111100;
            'd57 : sonuc <= 16'b0000001000101101;
            'd58 : sonuc <= 16'b0000001000011110;
            'd59 : sonuc <= 16'b0000001000001111;
            'd60 : sonuc <= 16'b0000001000000000;
            'd61 : sonuc <= 16'b0000000111110000;
            'd62 : sonuc <= 16'b0000000111100000;
            'd63 : sonuc <= 16'b0000000111010000;
            'd64 : sonuc <= 16'b0000000111000000;
            'd65 : sonuc <= 16'b0000000110110000;
            'd66 : sonuc <= 16'b0000000110100000;
            'd67 : sonuc <= 16'b0000000110010000;
            'd68 : sonuc <= 16'b0000000101111111;
            'd69 : sonuc <= 16'b0000000101101110;
            'd70 : sonuc <= 16'b0000000101011110;
            'd71 : sonuc <= 16'b0000000101001101;
            'd72 : sonuc <= 16'b0000000100111100;
            'd73 : sonuc <= 16'b0000000100101011;
            'd74 : sonuc <= 16'b0000000100011010;
            'd75 : sonuc <= 16'b0000000100001001;
            'd76 : sonuc <= 16'b0000000011110111;
            'd77 : sonuc <= 16'b0000000011100110;
            'd78 : sonuc <= 16'b0000000011010100;
            'd79 : sonuc <= 16'b0000000011000011;
            'd80 : sonuc <= 16'b0000000010110001;
            'd81 : sonuc <= 16'b0000000010100000;
            'd82 : sonuc <= 16'b0000000010001110;
            'd83 : sonuc <= 16'b0000000001111100;
            'd84 : sonuc <= 16'b0000000001101011;
            'd85 : sonuc <= 16'b0000000001011001;
            'd86 : sonuc <= 16'b0000000001000111;
            'd87 : sonuc <= 16'b0000000000110101;
            'd88 : sonuc <= 16'b0000000000100011;
            'd89 : sonuc <= 16'b0000000000010001;
            'd90 : sonuc <= 16'b0000000000000000;

endcase
end
end

    
endmodule


`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////



module TestBench();

reg clk,reset;
reg [7:0]count;
reg en;
TopModule uut(.en(en),.clk(clk),.reset(reset), .aci(count),.sonuc(sonuc));

initial begin
clk=0;
reset=0;
count<=0;
#100
en <= 1;
end

always@(posedge clk)begin
    if(reset)
    count<=0;
    else if (en)
    count<=count+1;
    end
    
always
#10 clk=~clk;


initial begin

#1810;
reset=1;
end

initial begin



#10;
count<=count+1;
end

endmodule
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