# Power Supply Input Filter

Can anyone explain why the two capacitors (C8, C9) in the CLC input filter are set up the way that they are? The screenshot is from this reference design:

https://www.ti.com/lit/df/tidryx8a/tidryx8a.pdf?ts=1610621203568&ref_url=https%253A%252F%252Fwww.ti.com%252Freference-designs%252Findex.html

I will provide some more context to my question:

I understand that there needs to be a smoothing capacitor on the output of that full-wave bridge rectifier to smooth rectified DC voltage. A rule of thumb of 2 - 3uF per watt of input power yields a value of 135uF - 405uF for Cin.

I also know that there needs to be an LC input filter to help mitigate differential-mode EMI.

According to TI's AN-2612 (linked below), the LC values are chosen based on equations outlined in section 4.2.

I cannot for the life of me figure out how we end up with those capacitor values (or inductor values for that matter) in that configuration. Can anyone offer their expertise?

https://www.ti.com/lit/an/snva489c/snva489c.pdf

• FWIW, C8, L1 and C9 form a pi low pass filter with cutoff frequency 3981Hz (if I did my math right.) Jan 15 '21 at 3:45
• Username checks out. How does that coincide with the input smoothing capacitor requirements to smooth out the rectified input? Jan 15 '21 at 3:59
• Well, rectified AC has a fundamental ripple component at 100Hz or 120Hz, and a third harmonic at 300Hz or 360Hz. So, this filter's cutoff frequency appears to be way too high to block either of these ripple components. So, I am left with the same question mark you have. Why these values? Jan 15 '21 at 4:23
• I'm thinking that the frequency of interest in this case is the frequency of the switching element, or 100kHz, and the particular L and C values were chosen to ensure that 100kHz noise is attenuated to some prescribed level. Jan 15 '21 at 4:54
• Yes, my conclusi is the same - the pi filter is mainly focused on dealing with EMI from the 100 KHz switcher. This still leaves me confused because I thought we still needed a smoothing capacitor to smooth the output of the full-wave bridge rectifier? Jan 15 '21 at 10:14

Can anyone explain why the two capacitors (C8, C9) in the CLC input filter are set up the way that they are?

The bulk capacitance (for the reduction of AC ripple) is, in effect both C8 and C9 in parallel = 94 μF. That's fundamentally the most important role they play and, in that respect, the 68 μH is incidental at these low frequencies. It might as well be a short circuit (about 0.05 Ω reactive).

Regards higher frequencies i.e. the switching noise produced by the SMPS, the inductor (L1) plays a significant role. As has been mentioned in comments, the cut-off frequency for the $$\\pi\$$-filter that it forms with C8 and C9 is 3981 Hz and, above that, the filter will attenuate frequencies in either direction. So, according to the source document, the switching frequency is 100 kHz and that means that switching artefacts will be reduced by about 56.2 dB due to the effect of the $$\\pi\$$-filter. So now the inductor is playing a vital role in cutting down the conducted emissions caused by the switching process.

A rule of thumb of 2 - 3uF per watt of input power yields a value of 135uF - 405uF for Cin.

That might be (not sure about this) a rule of thumb for conventional (linear) transformer/rectifier/capacitor power supplies but it doesn't cut-the-mustard on an SMPS because the chip that controls the thing is capable of running down to much lower input voltages whilst still supplying a regulated output.

One more thing to consider is that the smaller the bulk capacitors are (within operational reasons), the easier it is to acquire certification in terms of its power factor; big bulk capacitors do a great job of holding-up the DC bus voltage but do a terrible job with regards to the load current profile of the switcher from the AC terminals. In effect, big bulk value capacitors do not allow a design to meet modern power factor standards.

I'm not saying the TI design does meet these standards because I don't have access to the full tear-down of the design however, I have a suspicion that it does.

• Ok, this makes perfect sense to me now. Thank you! Jan 15 '21 at 10:52

Define converter input cap C and switching rate. Try method 1

1. Define isolated input noise voltage to estimate conducted noise

2. Use the input ripple Vin measured in a LISN (high impedance LC filter) to isolate the low impedance of the line and

3. compute the attenuation needed above 1uV minus the FCC limit Vmax.

• . Att|dB=20 log (Vin-ripple-p2p/ 1μV) - Vmax
1. Select filter inductance Lf.
2. Calculate filter capacitance Cf.
3. Calculate damping capacitance Cd
• Is damping capacitance the same thing as input capacitance (as in the smoothing capacitor that smooths the rectified output)? Jan 15 '21 at 4:03
• No it’s the 2nd C in CLC Jan 15 '21 at 4:05
• Where does the smoothing capacitor come in? Is there one in this schematic? Jan 15 '21 at 4:06
• L1 is the differential smoothing filter , L2 is the noise attenuator Jan 15 '21 at 4:25
• Ok, so I thought we needed a strong smoothing capacitor to smooth the output of the full-wave bridge rectifier? It does not appear that there is a capacitor like that in this circuit. Jan 15 '21 at 10:16