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I am trying to create a PMOS in Multisim based on a SPICE model.

The component itself is a DMC2400UV-7 from Diodes Incorporated (MOSFET N/P-channel array for 20V.)

The NMOS simulation didn't give me problems and it works as expected, but the PMOS when testing it as a switch does nothing, however, I see a voltage change in the base.

My testing circuit is this:

enter image description here

The full SPICE model is as follow:

*---------- DMC2400UV Spice Model ----------

*NMOS
.SUBCKT DMC2400UV_NMOS 10 20 30 
*     TERMINALS:  D  G  S
M1 1 2 3 3  NMOS  L = 1E-006  W = 1E-006 
RD 10 1 0.1925 
RS 30 3 0.001 
RG 20 2 68 
CGS 2 3 3.272E-011 
EGD 12 0 2 1 1 
VFB 14 0 0 
FFB 2 1  VFB 1 
CGD 13 14 6.7E-011 
R1 13 0 1 
D1 12 13  DLIM 
DDG 15 14  DCGD 
R2 12 15 1 
D2 15 0  DLIM 
DSD 3 10  DSUB 
.MODEL NMOS NMOS  LEVEL = 3  VMAX = 1E+006  ETA = 0.01  VTO = 0.9058 
+ TOX = 6E-008  NSUB = 1E+016  KP = 3.223  U0 = 400  KAPPA = 15.35 
.MODEL DCGD D  CJO = 1.94E-011  VJ = 0.1108  M = 0.3101 
.MODEL DSUB D  IS = 1E-009  N = 1.905  RS = 0.02633  BV = 25  CJO = 5.066E-012  VJ = 0.1753  M = 0.2672 
.MODEL DLIM D  IS = 0.0001 
.ENDS


*PMOS
.SUBCKT DMC2400UV_PMOS 10 20 30 
*     TERMINALS:  D  G  S
M1 1 2 3 3  PMOS  L = 1E-006  W = 1E-006 
RD 10 1 0.4041 
RS 30 3 0.001 
RG 20 2 14.3 
CGS 2 3 4.178E-011 
EGD 12 30 2 1 1 
VFB 14 30 0 
FFB 2 1  VFB 1 
CGD 13 14 5.7E-011 
R1 13 30 1 
D1 13 12  DLIM 
DDG 14 15  DCGD 
R2 12 15 1 
D2 30 15  DLIM 
DSD 10 3  DSUB 
.MODEL PMOS PMOS  LEVEL = 3  U0 = 400  VMAX = 1E+006  ETA = 0.001 
+ TOX = 6E-008  NSUB = 1E+016  KP = 1.095  KAPPA = 49.86  VTO = -0.8823 
.MODEL DCGD D  CJO = 1.311E-011  VJ = 0.2302  M = 0.2576 
.MODEL DSUB D  IS = 3E-009  N = 1.688  RS = 0.5  BV = 25  CJO = 6.498E-012  VJ = 0.3007  M = 0.2934 
.MODEL DLIM D  IS = 0.0001 
.ENDS

*Diodes DMC2400UV Spice Model v1.0 Last Revised 2014/11/18

For the NMOS I copied from *---------- DMC2400UV Spice Model ---------- to .ENDS and for the PMOS from *PMOS to .ENDS

Finally, the net definition is this one:

enter image description here

My ultimate intention is to fabricate 8 tristate pins (as the last image) to drive a high voltage Charlieplexed LED array.

enter image description here

Maybe I'm skipping something, maybe the SPICE model considers a symbol with 6 pins and not two of 3 pins.

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  • \$\begingroup\$ Do you want the PMOS conducting when the switch is closed and blocking when the switch is open or vice versa? \$\endgroup\$ – The Photon Jan 15 at 21:00
  • \$\begingroup\$ Just a heads up. That tri-state schematic is meant to be built using integrated circuit MOSFETs and not discrete MOSFETs. The difference is that the IC FETs have a 4th terminal (body), which is never explicitly shown in diagrams. The PMOS bodies are always connected to VDD and NMOS bodies always to VSS, unless shown otherwise. Since discrete FETs always have source shorted to body, you cannot connect QP11 and QN11 exactly as shown in the schematic. This might not matter for the tri-state buffer, but if you need to build other IC blocks from scratch, you might need something like an ALD1105. \$\endgroup\$ – Ste Kulov Jan 16 at 5:45
  • \$\begingroup\$ @SteKulov Thanks for your heads up. What would be the effect of connecting the body terminal of the inner MOSFETs to their respective sources? My point is, size is a restriction, and I haven't found a smaller IC than the ALD1105 that you proposed or even a matched pair only. \$\endgroup\$ – Smart_Celery Jan 18 at 15:16
  • \$\begingroup\$ @Smart_Celery I hear ya. I think it's less of an issue with a tri-state buffer so you can probably get away with it. I believe it doesn't cause that much of a discrepancy in that particular application, especially if you are never going to switch both IN and OE near the same time instant. I suggest spending some time making a good model of your pulse sources using Thevenin equivalents and rise/fall times representative of your CPU's GPIO. I did play around in SPICE with using VDMOS FETs for tri-states a long time ago, but I don't really remember the details. \$\endgroup\$ – Ste Kulov Jan 19 at 7:06
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To turn the PMOS transistor off you need to pull the gate up to the same voltage as the source. So, in your circuit you need a pull-up resistor from the gate to 12V.

Just opening up the switch doesn't change the voltage on the gate significantly, which is what you observed in your simulation. MOSFETs are voltage driven, unlike BJTs, so if the voltage doesn't change then the transistor will not behave differently.

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  • \$\begingroup\$ Thanks for your answer elliot, I'm quite sure I already did that (place a pull-up) but the simulation was crushing. Today I started from scratch and it worked flawlessly. \$\endgroup\$ – Smart_Celery Jan 18 at 9:09
  • \$\begingroup\$ @Smart_Celery Your schematic does not show a pullup resistor. Are you sure that you had one? \$\endgroup\$ – Elliot Alderson Jan 18 at 13:56
  • \$\begingroup\$ Hi Elliot, thanks for your answer. The schematic that I uploaded in this post does not have the pull-up. HERE you can see the latest schematic for the Tri-state driver. So far I have tested only two outputs but I need 8. \$\endgroup\$ – Smart_Celery Jan 18 at 14:05
  • \$\begingroup\$ @Smart_Celery Since the main issue driving the question has been resolved by this answer, I suggest accepting the answer and making new questions if needed. A couple tips since I have space. (1) It looks like those 5V sources are meant to model a CPU's GPIO, and if that's the case this is a very poor model. A better model would be to change the 5V to 0V when you switch from HIGH to LOW. A pulse source can make this easier. (2) Simulation is great, but it's not going to tell you the 12V through the pullup resistor can fry your CPU pin...especially with heavily simplified models like these. \$\endgroup\$ – Ste Kulov Jan 19 at 7:56

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