I am currently trying to learn how to program in VHDL with the goal of implementing an LDPC decoder in hardware. My understanding is that log-likelihood ratios (LLRs) serve as inputs to the decoder.
Is there an efficient way of reading from RAM if, for example, I have 1) 8-bit LLRs stored in a block of RAM that is 16 addresses deep, and 2) a 16-bit vector where a 1 in position X denotes that I want to read from address X.
As an example, given the 16-bit vector "1010100000000000", I would like to read from addresses 0, 2, and 4 (assuming that the LSB is on the left). My first thought is to use a loop through the entire vector, which seems inefficient in terms of clock cycles. Is there a way to quickly read from those three addresses, either in quick succession or in parallel?