Context: I'm prototyping an MIPI I3C Basic slave device implemented on a PSOC5LP. (I3C is similar to I2C, but is spec'd to run at up to 12.9 MHz.) Due to a speed limitation of the PSOC, I'm considering using external programmable logic (e.g. a 16V8) to implement one small part of the design. I'm looking for a more modern alternative to the 16V8 series parts.
The programmable logic on the PSOC can handle most of the timing requirements, but there is one spec'd clock-to-data timing that's hard to hit on the PSOC. The I3C spec calls this tSCO, see figure below.
For optimal operation, the I3C Basic spec says SCOmax is 12nS, but the best I'm likely to get out of the PSOC is > 23 ns. Reading up on available parts, it seems that at least some variants of the basic 16V8 PLD can achieve clock-to-output time of 10ns. That would do the trick, but it seems that in general 16V8s, and the like, are typically programmed out-of-circuit and require a CPLD programmer with specialized programming voltages and waveforms.
Question: Are there are alternative CPLD parts that can be programmed in-circuit, without programming voltages > 5V?
I'm thinking that a small FPGA might do, but it seems like overkill.
Note: the way SCOmax is defined, it doesn't include rise/fall times on the bus, but minimizing it gives the most headroom for the rise-time problems of bus capacitance.