Context: I'm prototyping an MIPI I3C Basic slave device implemented on a PSOC5LP. (I3C is similar to I2C, but is spec'd to run at up to 12.9 MHz.) Due to a speed limitation of the PSOC, I'm considering using external programmable logic (e.g. a 16V8) to implement one small part of the design. I'm looking for a more modern alternative to the 16V8 series parts.

The programmable logic on the PSOC can handle most of the timing requirements, but there is one spec'd clock-to-data timing that's hard to hit on the PSOC. The I3C spec calls this tSCO, see figure below.

Figure showing tSCO measurement

For optimal operation, the I3C Basic spec says SCOmax is 12nS, but the best I'm likely to get out of the PSOC is > 23 ns. Reading up on available parts, it seems that at least some variants of the basic 16V8 PLD can achieve clock-to-output time of 10ns. That would do the trick, but it seems that in general 16V8s, and the like, are typically programmed out-of-circuit and require a CPLD programmer with specialized programming voltages and waveforms.

Question: Are there are alternative CPLD parts that can be programmed in-circuit, without programming voltages > 5V?

I'm thinking that a small FPGA might do, but it seems like overkill.

Note: the way SCOmax is defined, it doesn't include rise/fall times on the bus, but minimizing it gives the most headroom for the rise-time problems of bus capacitance.

  • \$\begingroup\$ Perhaps it's just me but I am very confused by your question. You range from 16V8 to CPLD to PSoC to FPGA without really explaining what you are doing now. \$\endgroup\$
    – jwh20
    Commented Jan 17, 2021 at 22:12
  • \$\begingroup\$ Thanks @jwh20, I've updated the first paragraph to help explain. In short, the PSOC is a fixed choice, it may be augmented with a 16V8 (or FPGA) to meet a timing spec. \$\endgroup\$ Commented Jan 17, 2021 at 22:24
  • \$\begingroup\$ _"it seems that in general 16V8s, and the like, are typically programmed out-of-circuit and require a CPLD programmer with specialized programming voltages and waveforms." - eevblog.com/forum/microcontrollers/… \$\endgroup\$ Commented Jan 18, 2021 at 7:38
  • \$\begingroup\$ nz.element14.com/xilinx/xc9536xl-5vqg44c/… \$\endgroup\$ Commented Jan 18, 2021 at 7:44
  • \$\begingroup\$ Thanks @BruceAbbot, I learned a lot reviewing the xilinx datasheet. I guess JTAG programming was what I was really looking for. The xilinx part still seems like overkill, but I'm closer to knowing what I want. \$\endgroup\$ Commented Jan 18, 2021 at 23:06

1 Answer 1


I am not convinced that you really need programmable logic. The PSoC can update its data output ahead of time at the rising edge of the SCL, and use something fast to present that output on time to SDA when SCL falls. A tristate output D F-F, like 74LVC1G374 will do just that, with a propagation delay of 6ns max with 50pF load at 3.3V across temperature. Since the F-F needs to update on a falling clock edge, its clock input needs to be SCL inverted with e.g. 74LVC1G04, adding 3.3ns delay. You got 2ns to spare :)

If you want to drive larger capacitive loads, parallel a couple of those F-Fs. The inputs have 3pF typical input capacitance, so the maximum number of them in parallel depends on the allowed SCK unit load you can present.

You could probably make something a bit faster with discrete gold-doped switching transistors designed to stay fast even if driven into "saturation", but nobody makes those anymore, I don't think - and it'd be a power hog.

  • 1
    \$\begingroup\$ Ahh, thanks Kuba. I was looking for a component like that. When I looked at 74HC374, I concluded that octal FF was more than I wanted. Thanks for pointing this comes in a tiny single-gate package, I had never before encountered "1G" parts. I've learned something new. \$\endgroup\$ Commented Jan 22, 2021 at 23:19

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