# Verilog: Output propagation

I'm learning to use Verilog in a digital systems course. I have a question about value propagation.

I'll use the example below to ask my question.

module sampleModule
reg a,b,c;

not g1(d,b);
and g2(e,a,d);
and g3(f,c,e);

initial
a=1;b=1;c=0;

endmodule


I want to verify that my understanding of Verilog is correct: What I believe will happen right after time=0, when registers a, b, and c are loaded with the appropriate values is

1. Verilog will notify g1,g2,g3 that the values of registers a, b, c have changed.

2. In some indeterminate order

g1 will update its output value, d.

g2 will update its output value, e.

g3 will update its output value, f.

Gates will continue updating values until all are stable.

First off, is that right? Secondly, in the example above, the values will eventually stabilize, so Verilog is "happy" to update output values in any order. However, what if such is not the case and Verilog is given a poorly arranged feedback loop that alternates infinitely between two values? I understand that one can delay output propagation, but if not properly arranged, how does Verilog deal with an arrangement that should theoretically behave this way?

Yes, that is correct behavior of event driven simulation. But it can broken down even further. You update the value of a and g2 could update the value of e. And then either b gets updated, or g3 updates the value of f. Only the statements within the begin/end block have guaranteed ordering so that a must be updated before b, and b must be updated before c.
And yes, even with a simple nand g4(o,o,i); you can create an oscillation when i goes to 1. With a 0 output delay your simulation will hang. Most simulators catch this by placing a limit on the number of evaluations that can happen without time advancing. But with a non-zero output delay, o will oscillate until something else stops the simulation. The simulator has no way of knowing what the intent was; it does what you tell it to do.