I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.)
I tried to analyze their behaviors at the clock edges.
For D flip-flop 1,
At the rising edge, because the clock needs to go through one more NOT gate to reach the
master1latch, so I think the
master1latch will become opaque a little bit later than
slave1become transparent. That is, both D latches can be transparent at the clock "rise" for a short moment. As long as the D1 remain stable around the rising edge, the D will propagate all the way to Q1 as soon as
At the falling edge, for the same reason,
master1latch will become transparent a little bit later than
slave1latch becomes opaque. Q1 will be held by
slave1. So D1 won't affect Q1.
For D flip-flop 2,
At the rising edge,
master2becomes opaque a little bit earlier than
slave2becomes transparent due to the NOT gate. This is still OK for N2 to propagate to Q2 once
But at the falling edge,
master2becomes transparent a little bit earlier than
slave2becomes opaque because the CLK signal reaches
slave2. So it's possible that
master2turns transparent while
slave2also remains transparent. That is, both D latches can be transparent at the clock "fall" for a short moment. Thus Q2 may be contaminated by D2, which is not OK because
slave2fails to hold the Q2.
So the D flip-flop design 2 is bad.
Is my analysis correct? It seems the critical part is for the
slave D latch to respond to the clock faster than the
master D latch.. But I don't know yet how to quantify/specify this constraint. Most timing analysis I glanced so far focus on the rising edge. But I think the falling edge is also relevant.
ADD 1 - 9:27 AM 1/19/2021
I am digging into some materials about sequential circuit timing analysis. Will come back with some more info.