Analysis of two D flip-flop designs based on D latches

I am trying to create D flip-flops with D latches. Below are 2 possible ones. (Note that they are both rising-edge triggered.)

I tried to analyze their behaviors at the clock edges.

For D flip-flop 1,

• At the rising edge, because the clock needs to go through one more NOT gate to reach the master1 latch, so I think the master1 latch will become opaque a little bit later than slave1 become transparent. That is, both D latches can be transparent at the clock "rise" for a short moment. As long as the D1 remain stable around the rising edge, the D will propagate all the way to Q1 as soon as slave1 becomes transparent.

• At the falling edge, for the same reason, master1 latch will become transparent a little bit later than slave1 latch becomes opaque. Q1 will be held by slave1. So D1 won't affect Q1.

For D flip-flop 2,

• At the rising edge, master2 becomes opaque a little bit earlier than slave2 becomes transparent due to the NOT gate. This is still OK for N2 to propagate to Q2 once slave2 becomes transparent.

• But at the falling edge, master2 becomes transparent a little bit earlier than slave2 becomes opaque because the CLK signal reaches master2 sooner than slave2. So it's possible that master2 turns transparent while slave2 also remains transparent. That is, both D latches can be transparent at the clock "fall" for a short moment. Thus Q2 may be contaminated by D2, which is not OK because slave2 fails to hold the Q2.

So the D flip-flop design 2 is bad.

Is my analysis correct? It seems the critical part is for the slave D latch to respond to the clock faster than the master D latch.. But I don't know yet how to quantify/specify this constraint. Most timing analysis I glanced so far focus on the rising edge. But I think the falling edge is also relevant.

ADD 1 - 9:27 AM 1/19/2021

I am digging into some materials about sequential circuit timing analysis. Will come back with some more info.

• It all depends on the setup, hold, and propagation times of the latches. You should be able to create some formulas. For the fun part, grab some real-world data sheets and apply the values. Jan 22, 2021 at 11:08
• Recheck your analysis. Case 1 has overlap (both latches open) at clock rise, Case 2 does not (first stage closes before second stage opens.) Jan 27, 2021 at 21:02
• In the second case, Stage 1 has positive (helpful) skew that is in a race with the inverter, delaying the Stage 1 transition after the clock. This prevents shooting through. Jan 28, 2021 at 6:56
• The Stage 1 delay is at least 2 inverters when it’s open. The clock skew inserted by the inverter is only 1. So the clock wins the race, ensuring Stage 2 is closed before Stage 1 can propagate to it. Jan 28, 2021 at 7:17
• The skew inserted by the inverter is in the wrong direction. It neutralizes the beneficial delay of Stage 1. Jan 28, 2021 at 7:29

(ed. note: I try to not use the terms 'master' or 'slave' anymore, and instead use 'Stage 1' and 'Stage 2'.)

Case 1 has an increased hold time requirement, since both Stage 1 and Stage 2 have an overlap in their 'open' time due to the inverter delay. This overlap needs to be added to the hold time spec to ensure reliable operation.

That is,

• At clock low, Stage 1 is open, Stage 2 is closed
• At clock rise, Stage 2 opens. Stage 1 is still open => D could still change Q state (this is the overlap time)
• After inverter delay, Stage 1 closes.

Case 2 is a more typical design. Stage 2 is either clocked at the same time, or after Stage 1.

• At clock low, Stage 1 is open, Stage 2 is closed.
• At clock rise, Stage 1 closes => D has no effect
• After inverter delay, Stage 2 opens

Because of the inverter delay, there is no overlap of the open-time of the two latches. This means setup/hold is only determined by Stage 1. Stage 2 has its hold time met not only due to the inverter delay, but also due to the propagation delay of Stage 1 (more about this below.) This configuration however does have a longer clock-to-output delay than Case 1 due to the inverter delay.

There's a different way to think about latches: as a special case of multiplexers. The latch is in one of two states:

• Follow input (transparent)
• Hold

This can be constructed by using a 2-to-1 multiplexer, with one input tied to the data input, and the other tied to data output. Below is a D clocked-flop design, using multiplexers wired as hold/follow latches:

Simulate it here: D flip-flop using muxes

How it works:

• Stage 1 follows during clock low, and holds during clock high.
• Stage 2 follows during clock high, and holds during clock low

Notice that there's no inverter (more about that in a bit.) Stage 2 and Stage 1 switch from hold to follow and vice-versa at the same time. The propagation delay from Stage 1 select to Q ensures the hold time for Stage 2, such that there is no overlap. Again, only Stage 1 needs to be considered for setup time.

This mux style of logic is more typical for a CMOS design, because it's easy and efficient to make a structure called a transmission gate.

Here's a more detailed look at a CMOS mux-based D-flop using transmission gates. Notice that the level sensitivity only depends on how the switches are wired up: this could be made negative-edge by either swapping the clock phases or swapping the mux inputs.

And hold time? Still only dependent on Stage 1. Note that there's two inverter delays from Stage 1 Q to Stage 2 D, while there's only 1 inverter delay for the clock. So it's impossible for the latches to overlap.

Simulate it here: Discrete CMOS mux-based D-flop

More about CMOS flip-flop structures here: http://ece-research.unm.edu/jimp/vlsi/slides/chap5_2.html

• Nope. The added delay of Stage 1 covers the shoot-through case. Jan 28, 2021 at 7:14

The timing constraints for the D Flip-Flop constructed using D latches to work are:

$$\t_{ccq(initiator)} >= t_{hold(follower)}\$$

$$\t_{ccq(initiator)}\$$ represents the clock-to-q contamination delay of the initiator latch.

$$\t_{hold(follower)}\$$ time is the hold time of the follower latch.

Dummy logic (such as 2 inverters in series) could be inserted at the output of the initiator to meet the timing requirement.

• The timing constraints for the first circuit to work are: $$\t_{ccq(initiator)} + t_{cd(inverter)} >= t_{hold(follower)}\$$

• The timing constraints for the second circuit to work are:

$$\t_{ccq(initiator)} >= t_{cd(inverter)} + t_{hold(follower)}\$$

1. D Flip-Flop using latch with positive enable
Simulate this circuit on Multisim Live: D Flip-Flop using latch with positive enable

2. D Flip-Flop using latch with negative enable
Simulate this circuit on Multisim Live: D Flip-Flop using latch with negative enable