Electrical Engineering Stack Exchange is a question and answer site for electronics and electrical engineering professionals, students, and enthusiasts. It only takes a minute to sign up.
Sign up to join this community
Many publications, when they speak about a single transistor, the maximum and cut-off frequencies are way higher than of the final circuit.
Example: A modern FinFET, some report a maximum oscillation frequency of 150GHz or higher. On the other hand, a CPU runs at only at a base clock of 3GHz.
What is the difference?
If you have any bibliographic references that answer this in detail, could you please share them?
A CPU's logic design is highly tuned to minimise the number of gates between registers (made of flip-flops); some CPUs have 12 or 14 or 16 gates on the longest path. That means a signal has to propagate through 2 FFs, 13 wires and 12 amplifiers (gates) before the next clock pulse.
(This paper suggests the optimal would be 6 to 8 gates before the FF delays started reducing performance : scanning it, it appears to be a hypothetical paper, and I haven't heard of any practical CPU with as few as 10 gate delays. I vaguely recall Andy Glew upset a lot of fast RISC CPU designers when his Pentium Pro at about 12 gates upset most expectations of what an x86 CPU could do)
So one shouldn't expect it to work at clock frequencies more than about 1/25 the speed you can get a single element to oscillate.
That would get you down from 150GHz to maybe 6 GHz right there; but it's clearly not the whole story.
Given millions of elements on a CPU, you can't afford to power them as much as you can a single transistor, both from power supply and interconnection issues, and from thermal (heat dissipation) issues. So they are tuned to somewhat less than the maximum power (and higher speed requires higher power)
150Ghz or higher. while -for example- a CPU runs at only at a base clock of 3Ghz.
Well, a CPU isn't a single transistor; it's billions, and even the speed of light wouldn't allow for a CPU core to distribute a clock consistently across a die at 150 GHz.
It gets worse, though: your transistor might switch incredibly fast, but it has to (dis-)charge the gate of the next transistor, and since even in fully switched state, your drain-source impedance isn't 0 Ω, and your power supply can't supply infinite current that simply takes time.
Now, a single transistor doesn't make a logic gate, you need multiple; a single logic gate doesn't make a complex unit such as floating point multiplier, you need hundreds. So, you get complex networks of connected gates and typically CMOS pairs. There's going to be a longest path there, which simply takes a lot of time from the first CMOS pair switching to the last CMOS pair switching. That's the ultimate limiting factor: you can't get faster than that, even if you ignore all other problems.
(I don't think you actually need a bibliographic reference to that, that's kind of "common knowledge"; else, pick your arbitrary VLSI textbook.)
And there's plenty of other problems: You can't increase voltages to speed up charging of gates, simply because ohmic losses go with the square of your voltage, and ho boy, is your CPU thermally limited.
You can't work with a "oh, it doesn't have to be at 99% of supply voltage, 80% is enough charge that is achieved within a cycle", because, again, billions of transistors: Reducing the "acceptable threshold", then you get cascading probabilities of things not being in the correct state. Do that a billion time at once, and you basically guarantee that something goes wrong in your CPU.
Atop of that, you, being a TCAD engineer, will definitely have to deal with a lot of interactions that say "many transistors on a die do not behave like a lot of independent transistors".
Many publications, when they speak about a single transistor, the maximum and cut-off frequencies are way higher than of the final circuit.
Think about what \$f_{\mathrm{max}}\$ actually means. It is the frequency at which the transistor has unity power gain. In other words the transistor cannot be considered an active device above this frequency. In practise this limits the operation frequency to at most half of \$f_{\mathrm{max}}\$, since you actually want to have a reasonable power gain for the transistor to be useful.
The book "High-Frequency Integrated Circuits" by S. Voinigescu even states:
"Over the years, circuit designers have established an empirical rule that transistor \$f_{MAX}\$ values four to five times higher than the frequency of operation of the circuit are needed to develop robust, high-yielding commercial ICs. For example, today’s first commercial 77GHz automotive radar and 60GHz radio transceivers are fabricated in technologies with transistor \$f_{MAX}\$ values in the 250–300GHz range."
Today there is research done in a lot of fields where operation frequencies up to hundreds of GHz are a reality. But this still requires for the transistor to have a several times larger \$f_{\mathrm{max}}\$ and transistors like that do exist.
Large CPUs are not a good example for a comparison with the technology's transistor \$f_{\mathrm{max}}\$ because there are reasons like power dissipation (density) putting a much lower limit to the operating frequency. In RF circuits the number and density of transistors is a lot lower so that power dissipation, in terms of cooling the chip, is less critical.
