# How to get a 1 clock period pulse from a constant signal clock input on every 64 clocks?

I would like to "extract" a one period pulse from a constant clock signal on every 64 clocks. This pulse signal is to be used for reset. What kind of logic circuit should I be looking for? Thank you.

• Voltages? Frequency? Phase relationship requirements? Commented Jan 18, 2021 at 20:33
• @Elliot Alderson The voltage is 0-5V. Frequency of the clock will vary between 1Hz - 20Hz. Extracted pulse must be in phase with the clock. Thanks. Commented Jan 18, 2021 at 20:53
• How much phase difference, in nanoseconds, can you tolerate between the input clock and the output pulse? Commented Jan 18, 2021 at 21:37
• Just to clarify if you would please, is the extracted pulse to be the width of just the high phase of the clock pulse or the width of one complete clock period that is to say the width of both the high phase and the low phase combined.
– user173271
Commented Jan 19, 2021 at 3:04
• @James Just the high phase of the clock. Thanks. Commented Jan 19, 2021 at 22:07

I have assumed that you just want a high pulse out during the high phase of the clock every 64th clock pulse.

4024 is a negative edge triggered 7 stage binary counter. 4068 is an 8 input Nand gate. 4013 is a Dual D-Type flip flop.

Output of nand gate is usually high holding D type flipflop in reset. On a certain falling edge of the clock, the counter will increment to all ones output. The nand output goes low releasing the reset on the flipflop. The next rising edge of the clock clocks a one through to the Q output of the flipflop. The next falling edge of the clock makes the Q1 to Q6 outputs roll over to all zeros, the nand gate output goes high reseting the flipflop.

• One minor point. It's generally not a good idea to drive an asynchronous input (the R input to the FF in this case) from combinatorial logic like the NAND gate you showed. The output of the NAND gate could have glitches on it's output, due to path length differences within the NAND gate or prop delays through the counter that would cause the DFF to reset. If the reset input was synchronous WRT the clock, then you would be OK with what you've shown. Commented Jan 18, 2021 at 23:15
• @SteveSh I did consider that. The nand gate output is high most of the time holding the flipflop in reset as required. Any glitches on the counter or nand gate outputs will momentarily release the flipflop's reset (but not set the flipflop). The nand gate output will settle in a state that holds the flipflop in reset after each increment of the counter. The flipflop is positive edge triggered where as the counter is negative edge triggered so the 1 on the D input will not be clocked through to the Q output during any short glitches on the flipflop's reset input.
– user173271
Commented Jan 18, 2021 at 23:46
• If you want one clock period, you can just invert the output of the NAND gate and you are done. Feed it through one or two stages of DFF to re-register it to the clock (if desired). The RS flip-flop is shortening the pulse to half a clock period instead of one clock period as was requested in the OP. Commented Jan 19, 2021 at 1:48

Ripple counter, and a one-shot trigger type thing if you want to shorten the extracted pulse.

• And here's a list of logic circuits from which you could find a suitable IC: en.wikipedia.org/wiki/List_of_4000-series_integrated_circuits Commented Jan 18, 2021 at 20:30
• Yup, and consider more modern logic families like 74LVC if you desire better rise times and what not. 4000 series can handle higher voltages though, if that's what you want. Commented Jan 18, 2021 at 20:31
• @syntax Could you explain what do you mean by "one-shot trigger"? A monostable circuit/chip? Thanks. Commented Jan 18, 2021 at 20:56
• Sorry for the late reply - take a look at the various configurations of the 555 chip. Commented Jan 18, 2021 at 22:15