-1
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There are just 6 errors now

Can't trace errors in this VHDL

entity clothes_washer is
port(
--inputs
clk: in std_logic;       --Clock 50Mhz
start_wash: std_logic;   --SW17
heat_dry: std_logic;     --SW14
Door_open: in std_logic; --SW0
reset: in std_logic;     --KEY3
fifty_cent: in std_logic;  --SW15
twenty_cent: in std_logic;  --SW16

--outputs
door_lock: out std_logic;  --LED0
water_pump: out std_logic; --LED1
soap: out std_logic; --LED2
rotate_drum:out std_logic; --LED3
drain: out std_logic; --LED4
heat: out std_logic; --LED5
air_ventilate: out std_logic; --LED6
check: out std_logic; --LEDG7, to proof the ongoing process

);
end Clothes_washer

architecture Behavioral of Clothes_washer is
TYPE state_type IS (zero,one,two,three,four,five,six,seven,eight,nine);
SIGNAL state: state_type:=zero;

begin
next_state_logic: process(clk)

begin
if(clk' event and clk='1') then
case state is

when zero=>
-----------------------Washer------------------
if(fifty_cent = '1' and twenty_cent='0') then
    if(door_open = '0') then
        check<='1';
        if (start_wash='1' and heat_dry= '0' ) then
            state<= one;
        else
            state<= zero;
        end if;
    else
        state<=zero;
    end if;

-----------------------Dryer------------------
if(fifty_cent = '0' and twenty_cent='1') then
    if(door_open = '0') then
        if (start_wash='0' and heat_dry= '1' ) then
            state<= eight;
        else
            state<= zero;
        end if;
    else
        state<=zero;
    end if;
----------------------------------------------
---STATES-----
when one =>
state<=two;

when two =>
state<=three;

when three =>
state<=four;

when four =>
state<=five;

when five =>
state<=six;

when six =>
state<=seven;

when seven =>
state<=zero;

when eight =>
state<=nine;

when nine =>
state<=zero;

end case;
end if;
end process;

------------------------------------------------
--------OUTPUT----------

output_logic:process(reset,state,clk)
begin
if reset = '0' then
case state is

when zero=>
door_lock<= '0';
water_pump<='0';
soap<='0';
rotate_drum<='0';
drain<='0';
heat<='0';
air_ventilate<='0';

when one=>
door_lock<= '1';
water_pump<='1';
soap<='1';
rotate_drum<='0';
drain<='0';
heat<='0';
air_ventilate<='0';

when two=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='1';
drain<='0';
heat<='0';
air_ventilate<='0';

when three=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='0';
drain<='1';
heat<='0';
air_ventilate<='0';

when four=>
door_lock<= '1';
water_pump<='1';
soap<='0';
rotate_drum<='0';
drain<='0';
heat<='0';
air_ventilate<='0';

when five=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='1';
drain<='0';
heat<='0';
air_ventilate<='0';

when six=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='0';
drain<='1';
heat<='0';
air_ventilate<='0';

when seven=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='0';
drain<='1';
heat<='0';
air_ventilate<='0';

when eight=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='1';
drain<='0';
heat<='0';
air_ventilate<='0';

when nine=>
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='1';
drain<='0';
heat<='1';
air_ventilate<='1';

end case;
elsif reset='1' then
door_lock<= '1';
water_pump<='0';
soap<='0';
rotate_drum<='0';
drain<='0';
heat<='0';
air_ventilate<='0';

end if;
end process;

end Behavioral;

Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")";  expecting an identifier, or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at clothes_washer.vhd(26) near text ")";  expecting ":", or ","
Error (10500): VHDL syntax error at clothes_washer.vhd(29) near text "begin";  expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"
Error (10500): VHDL syntax error at clothes_washer.vhd(97) near text ")";  expecting ":", or ","
Info (12021): Found 0 design units, including 0 entities, in source file clothes_washer.vhd
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 4 errors, 1 warning
    Error: Peak virtual memory: 4680 megabytes
    Error: Processing ended: Tue Jan 19 12:10:55 2021
    Error: Elapsed time: 00:00:01
    Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 6 errors, 1 warning

enter image description here

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8
  • \$\begingroup\$ electronics.stackexchange.com/questions/543310/… \$\endgroup\$
    – STUDENT
    Jan 19 at 4:49
  • \$\begingroup\$ You can view the actual text here. Im not familiar with this site. So I dont know how to paste the text in code form . \$\endgroup\$
    – STUDENT
    Jan 19 at 4:50
  • \$\begingroup\$ Done Sir. Please help me \$\endgroup\$
    – STUDENT
    Jan 19 at 5:03
  • \$\begingroup\$ now do the same with the error printout ... place ``` on a line before the printout and also on a line after the printout \$\endgroup\$
    – jsotola
    Jan 19 at 5:07
  • 1
    \$\begingroup\$ Your first error is that the last line in your port shouldn't end with a semi-colon. I know, it's a stupid thing VHDL requires but you have to do it. Should just be: check : out std_logic ); Once one error is found the compiler often will stumble on the remainder so fix the the first problem first, recompile and see what's left. \$\endgroup\$
    – td127
    Jan 19 at 6:15
6
\$\begingroup\$

This is not specific to VHDL, but generally here's how to interpret compiler error messages:

Error (10500): VHDL syntax error at clothes_washer.vhd(22) near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"

The keyword "Error" means a serious problem that prevents the program from even being built. Other types of messages you could see are "Warning" (the design can be built, but something looks very wrong), and "Info" (just neutral information about the build).

"syntax error" means that there's something wrong with the way the source code is entered... semantics is meaning of language, and syntax is structure of language. A statement like "I have a red sofa" conveys incorrect information but still has valid syntax, but a statement like "Idnz wefk 33, !##sfo" doesn't even have understandable syntax. The compiler is complaining that it can't make any sense of what's at that point.

"clothes_washer.vhd(22)" identifies the offending source file and which line number the compiler had reached when it realized there was an error. The actual error could be on that line, or maybe on the line just before it. Line numbers are important for locating error reports, make sure you are using a text editor that displays line numbers and lets you go directly to a specific line number. Counting down 22 lines isn't so bad, but trying to locate an error on line 2374 is too many to count by hand.

01: entity clothes_washer is
02: port(
03: --inputs
04: clk: in std_logic;       --Clock 50Mhz
05: start_wash: std_logic;   --SW17
06: heat_dry: std_logic;     --SW14
07: Door_open: in std_logic; --SW0
08: reset: in std_logic;     --KEY3
09: fifty_cent: in std_logic;  --SW15
10: twenty_cent: in std_logic;  --SW16
11: 
12: --outputs
13: door_lock: out std_logic;  --LED0
14: water_pump: out std_logic; --LED1
15: soap: out std_logic; --LED2
16: rotate_drum:out std_logic; --LED3
17: drain: out std_logic; --LED4
18: heat: out std_logic; --LED5
19: air_ventilate: out std_logic; --LED6
20: check: out std_logic; --LEDG7, to proof the ongoing process
21: 
22: ); -- VHDL syntax error near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable"
23: end Clothes_washer
24: 
etc.

So now with line numbers displayed, you can see that the actual problem was at the end of this entity declaration, near the closing ")".

This particular error message goes on to say: near text ")"; expecting an identifier, or "constant", or "file", or "signal", or "variable" -- as noted in a comment from user td127, VHDL compiler does not expect to see ";" at the end of the last port item. Since there was a semicolon, and semicolons only come between port items, it was expecting another port declaration, instead of the end of the list... What you have right now is similar to

entity xyz is port(a: in std_logic; b: out std_logic;);

which is wrong syntax, it should be

entity xyz is port(a: in std_logic; b: out std_logic);

The exact punctuation is really important. The compiler cannot just figure out what you meant. If the punctuation isn't perfect, it will throw a syntax error.

There are several other places where you have the same mistake, check line 26, and line 97; and there's a different kind of mistake on line 29 near or just before the "begin". Are you sure that's the right place to declare type state_type? It looks like signal declarations are allowed between "architecture" and "begin" but I don't see evidence that type declarations are valid there. (I'm not a VHDL expert, I'm more used to Verilog, but just skimming a few quick reference guides, https://owd.tcnj.edu/~hernande/r/VHDL_QRC__01.pdf and http://atlas.physics.arizona.edu/~kjohns/downloads/vhdl/VHDL_Lang.pdf)

Bring up your favorite internet search engine and put the core of the error message into the search text: "VHDL syntax error near ")"" and you will find some useful information... sometimes there are many possible causes of an error message, so you may have to chase down several leads to find it...

Questions like "here's my code, plz help" are never well received... It's better if you can be more specific, like this:


VHDL syntax error near text "begin"; expecting an identifier

I'm getting this error message:

VHDL syntax error at clothes_washer.vhd(29) near text "begin"; expecting an identifier ("begin" is a reserved keyword), or "constant", or "file", or "signal", or "variable"

This is the context:

architecture Behavioral of Clothes_washer is
TYPE state_type IS (zero,one,two,three,four,five,six,seven,eight,nine);
SIGNAL state: state_type:=zero;

begin -- line 29 VHDL syntax error near text "begin";  expecting an identifier
next_state_logic: process(clk)

begin
if(clk' event and clk='1') then
case state is

And in fact, if you search for VHDL syntax error near text "begin"; expecting an identifier there are already a lot of similar questions posted, so it's worth looking at those before posting a new question.

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1
  • \$\begingroup\$ The semicolons between port list element declarations are a separator not a delimiter. The parser has a look ahead of one. The incorrectly included semicolon expects another port list declaration which can be preceded by the optional reserved word signal or would begin with a signal name (an identifier). A similar issue can occur with commas in association lists. Commas are separators as well. \$\endgroup\$
    – user8352
    Jan 19 at 18:42

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