I have a digital down counter which is supposed to count from 9 to 0 and then it goes back to 9 (bottom) but it only goes back from 9 to 8 and then back to 9 and I don't understand how it works.

Note that before I made that circuit I had connected the inputs of the gates to Qbar without a NOT gate of each JK flip flop but it counted until 1 so it didn't make the job it had to make.

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What am I missing?

  • \$\begingroup\$ It's quite difficult to follow your schematic but I think your issue is that you're always setting a "0" on the output of the 4-input AND gate which is, I assume, setting/resetting the JK FFs on every clock. But you're left a LOT to the imagination here. \$\endgroup\$
    – jwh20
    Jan 20 '21 at 16:33
  • \$\begingroup\$ Are the set/reset of your flip-flops synchronous or asynchronous? \$\endgroup\$ Jan 20 '21 at 17:12
  • \$\begingroup\$ They are asynchronous. \$\endgroup\$
    – Clone Wars
    Jan 20 '21 at 17:30

The problem is a glitch on the outputs when the counter tries to go from 8 to 7. There is an intermediate glitch state of 1111 when the 3 left flipflops' Q outputs have all changed state to 1 but the right hand flipflop's Q output has not quite changed state, it is still at 1. The And gate decodes this all 1's glitch (all zeros on the ~Q outputs) and resets the flipflops to 9.


Add an extra stage to the counter as shown below. Then when the lower 4 bits transition from 8 to 7, the extra most significant bit will be zero and the And gate will not generate a glitch pulse. Of course you'll generate the same problem if you try to reset the counter to a value greater than 15 because the And gate will produce a glitch output when the counter tries to step from 16 to 15.

Down counter

  • \$\begingroup\$ How do I solve it? \$\endgroup\$
    – Clone Wars
    Jan 20 '21 at 17:31
  • \$\begingroup\$ Design a synchronous down counter. \$\endgroup\$
    – James
    Jan 20 '21 at 17:33
  • \$\begingroup\$ The JK flip flop reset/set pins are asynchronous. \$\endgroup\$
    – Clone Wars
    Jan 20 '21 at 17:37
  • \$\begingroup\$ I don't think synchronous set/reset would help solve the problem on an asynchronous down counter. If you used synchronous reset/reset and decoded for 0000 on the Q outputs there would still be a problem because the first flipflop would be set when it received its clock pulse removing the decoded output signal before the last flipflop received its clock pulse. I've never actually designed an asynchronous down counter with JK flipflops which have synchronous set/resets though. \$\endgroup\$
    – James
    Jan 20 '21 at 18:00
  • \$\begingroup\$ @Clone Wars See edited solution \$\endgroup\$
    – James
    Jan 20 '21 at 23:58

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