I am performing SI analysis for the GTX transceiver interface. the FPGA that I am using is Xilinx Kintex-7 FPGA. I have received a reference SI analysis report done by customer which has eye width, height extra details. Can someone please help me out in understanding how is the minimum eye height other values obtained are decided that their within the specification. I will be following SATA 3.0 protocol. My signal rate is 6GB/s.