What causes the Inverting input of this op amp to conduct current?

Question

When I analyse this circuit to understand it's working, I got stuck at one point. Have a look on this circuit. When the feedback resistor value is 2.2k as shown in fig, I got the expected output with the DC offset at the output pin. There is some nA of current flow at the inverting input pin of this Op-Amp. There is only 3mVrms voltage at the inverting input.

When I increase the feedback resistor to 100k, the gain also get increased. I understood. Due to that, output signal also get clipped since the voltage swing is limited to 5V at the positive and negative side.

The intriguing part is the inverting input of the op amp. After increased the gain to 100k, significant amount of current up to some micro Amps of current starts to flow. This causes around 3.3 Vrms drop at the inverting input side.

The question is, why current flow increases at the inverting input pin after increases the gain of the op amp via feedback resistor. What happens there?

Also, I could not bring the voltage drop of 3Vrms at the inverting input via calculation.

Kindly help me to understand!!!

Answer 1

With the op-amp hitting its rails, it can no longer hold its inverting output equal to its non-inverting output through feedback.

First, there's no guarantee (unless the datasheet says so) that when there's a large differential-mode voltage across the inputs that the pins won't draw lots of current.

Second, you're driving the thing from a supply in excess of 500VRMS. I would expect that you're bringing the inverting input to the power supply rails, alternating between VCC and VEE. In that situation then of course the chip will draw current -- in most chips, you can just assume that if you bring an input above VCC or below VEE that current will flow.

So -- use your op-amp as an op-amp, and it'll be happier.

I would suggest that since you're obviously dropping voltage here, and since the input is larger than the power supply, that you use a voltage divider followed by a much smaller gain. I'd design things so that with the op-amp removed from the circuit none of its pins will be driven outside the range \$V_{EE} \le v \le V_{CC}\$. That way you know that even if there's a component failure somewhere, you're much less likely to let huge voltages into your circuit.