Debounce slide switches in verilog?

Question

I just created my first FPGA project. I created a small FPGA PCB with some slide switches to input values to the FPGA. Sadly, I did not debounce them properly with hardware, as you can see in these oscilloscope images:

How can I debounce the switches in "soft"ware on the FPGA? I found some examples online, but they didn't work for me. My internal clock is 16MHz.

Edit: I am using a TinyFPGA Bx module. According to the datasheet, the inputs are built with Schmitt-Triggers. Looking at the images of the osci, those „steps“ are weird behaviors between slide switch and input. For hardware debouncing, I used a 10k resistor and 10n capacitor. The wierd voltage rise / fall creates some wierd Fpga behavior. Why could that be and how could one filter the signal to be „just one jump“?

Edit: Solution: My clock was not unbounced. I solved it using Verilog.

Answer 1

I doubt you have issue in your Verilog code , and you say that weird behavior. The oscilloscope images seems normal. Try this simple example :

Switches to LEDs

`timescale 1ns / 1ps

module top(
    input [3:0] switches,
    output [3:0] leds
    );
    
    assign leds = switches;
endmodule

Remember to add constraint file for the switches and LEDs.

Still if you need to debounce switches, The easiest way to debounce switches / Push buttons in Verilog is to use Slow clock. In order to achieve a slow clock , you have to use a clock divider , divide your 16MHz clock into something slower like 8MHz or 4MHz. With a slower clock you'll be able to catch the event.

Read this Article

Answer 2

I won't opine on whether the problem is your debouncing or not. I will just tell you how to debounce something in FPGAs (works in software too).

Conceptually, there are two simple debounce methods you can do when making a debounce block:

1. On an incoming edge, immediately pass the signal state to the output and latch that output for n-cycles. Low latency since it reacts immediately, but is sensitive to induced noise.

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2. More immune to induced noise but higher latency is to block the incoming edge from affecting the output until the input is stable for n-amount of cycles.

The clumsy way to do this is to store all the previous N-samples in a rolling state and compare them to make sure they are all the same before passing on the input to the output. Each time you grab a new sample, you throw out the oldest sample (shifts are good for this).

Don't use that method. It takes up a lot of memory if your clock is running very fast (which it probably will be) compared to the mechanical settling time of the switch since you require many more samples for the same amount of settling time.

The more efficient way is to store only the previous sample and compare it to the current sample and if they are the same increment a counter. Then pass the input to the output only if the counter exceeds a threshold. If current and previous sample are ever different, reset the counter. That way you can compare the previous samples for the previous billion cycles if you wanted to without needing to store the previous billion samples. It goes without saying that every time you are finished comparing current and previous sample, you update the previous sample with the current sample.

And like, all signals coming into your FPGA that are not synchronized to your FPGA's clock, do not forget to run them through a chain flip-flops before doing ANYTHING (including debouncing) with them.