) I've always wondered what will happen with CMOS transistor in the IC if it is exposed by over-current or over-voltage? I mean what are the possible outcomes. Will the CMOS be like in short circuit, circuit break or some intermediate state with some sort of an arcing maybe... Will it be always closed or always opened? Or maybe its channel resistance will change... For example let's suppose that we consider two digital CMOS integrated circuits with push-pull outputs working on each other (directly connected without serial resistors). Can something bad happen? And how can I diagnose the outputs state with a multi meter in that case? Thanks!)

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    \$\begingroup\$ Not all cmos ics are the same! Possible outcomes? Many and varied. Generally, if two outputs are fighting, then you’ll get an intermediate logic level. Sone parts may tolerate this, some might not. \$\endgroup\$
    – Kartman
    Jan 25, 2021 at 2:29
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    \$\begingroup\$ You assume that a transistor will be damaged. Why do you assume that? There's way more possibilities than just a transistor, so asking about specific failure type (of a transistor) better had some background that justifies this question, because I smell an XY problem: you really want to ask something else, but focus on the transistor as some sort of an "approachable" detail. \$\endgroup\$ Jan 25, 2021 at 14:39
  • \$\begingroup\$ Well, I just wondering what can happen, and specifically consider two push-pull CMOS IC's outputs of digital (3.3V) circuit. I just want to deep dive into inner front-end circuitry of such ICs and get better understanding of how it works... \$\endgroup\$
    – Andy
    Feb 6, 2021 at 11:27

1 Answer 1


Answering this question is akin to opening Pandora's box.

In general a CMOS transistor will be ruined by over-current or over-voltage by breakdown of the gate oxide. Normally, the gate should be isolated from the channel/drain/source, but after breakdown a low-resistive path can be created which hinders the normal operation. From what I can find, it appears that injection of carriers across the barrier (Fowler-Nordheim tunneling) and the creation of traps/states throughout the oxide layer lie at the base. At some point there seems to be a positive feedback effect that accelerates this trap creation, which increases current, which accelerates trap creation, etc. The end result of this process would be more or less a short-circuit from the gate to semiconductor. Due to the rapid heating, the gate can even be physically destroyed.

How the transistor fails can also vary pretty wildly. There are cases where it doesn't completely destroy the transistor:

Chih-Hang Tung, K. -. Pey, L. J. Tang, Y. Cao, M. K. Radhakrishnan and W. H. Lin, "Fundamental narrow MOSFET gate dielectric breakdown behaviors and their impacts on device performance," in IEEE Transactions on Electron Devices, vol. 52, no. 4, pp. 473-483, April 2005, DOI: 10.1109/TED.2005.844763.

If you're serious about figuring this out, you'll probably need to start analyzing literature.

J.F. Verweij and J.H. Klootwijk, "Dielectric breakdown I: A review of oxide breakdown" Microelectronics Journal, Volume 27, Issue 7, 1996, Pages 611-622, DOI: 10.1016/0026-2692(95)00104-2

B. Peŝić, S. Dimitrijev, N. Stojadinović, "Investigation of gate oxide breakdown in CMOS integrated circuits", Microelectronics Journal, Volume 20, Issue 6, 1989, Pages 19-26, DOI: 10.1016/0026-2692(89)90064-5.

  • \$\begingroup\$ Thank you, Sven B!) Your answer is really helpful!) Well, yes, it sounds pretty complicated and I definitely should search through some literature, thank you for the references also. Well, the last question, how do you think (if we consider the case of two CMOS push-pull outputs fighting), Can the over-current that will happen in this case be the cause of the gate oxide breakdown and how? I thought the exceeding channel current can only damage the channel itself by heating it. \$\endgroup\$
    – Andy
    Feb 6, 2021 at 11:19
  • \$\begingroup\$ And also (the very last one) well, how do you think, fighting push-pull CMOS outputs can damage each other in general case? I think, open CMOS has ~100Ohm resistance, so 3.3/200 = 16 mA - which can be the limit for some ICs. Is my train of thought right? Thanks! \$\endgroup\$
    – Andy
    Feb 6, 2021 at 11:22
  • \$\begingroup\$ High energy electrons can still damage the oxide and reduce the lifetime. Fighting push-pull CMOS outputs don't necessarily break the circuit, it depends on the design (sizing, heat sinking capabilities, routing). It seems to me that you are trying to find a general reason for something that is (more often than not) context-dependent and nuanced. \$\endgroup\$
    – Sven B
    Feb 8, 2021 at 8:45
  • \$\begingroup\$ Ok, thank you! I'm more than satisfied with the answer. \$\endgroup\$
    – Andy
    Feb 14, 2021 at 10:02

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