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I read AN-5073 Active Miller Clamp Technology | Fairchild Semiconductor, and was wondering about what the possible disadvantages could be if a PNP transistor is used to bypass the Miller current as shown in the application note.

Would the increase of stray loop inductance be a possible problem since a PNP transistor will need some space to be put on the board, and that means the gate driver IC would be a bit further away from the main IGBT or MOSFET?

This is the part from the document I was asking about (Fig.5, p.2):

enter image description here

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    \$\begingroup\$ Would the increase of stray loop inductance be a possible problem Everything's possible and everything can be a problem. So what to do? Quantify it, that means, put some numbers on the issue and do calculations and/or simulations to prove that it is a problem or not. A track of 1mm has about 1 nH of inductance so you could make a guess what the inductance will be. Then simulate that and see if the inductance matters (make the inductance zero and compare that to a more realistic value). The faster you switch the more of an issue any inductance is going to be. \$\endgroup\$ Commented Jan 24, 2021 at 18:50
  • \$\begingroup\$ @Bimpelrekkie, Ah yes, so I have heard the comment: "Talk is cheap, show me the numbers". Cheers \$\endgroup\$
    – tlfong01
    Commented Jan 25, 2021 at 0:22

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The faster switching might cause problems with the existing inductance in the source, dragging Vo below ground through Rg and killing the driver chip.

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The increased loop length to gate driver is acceptable, because less I and dI/dt flows through it, at least on the falling edge. The driver sinks little current, and what's actually doing the driving (the PNP) is much closer -- as close, or perhaps even closer than the driver would be otherwise.

The increased loop for the rising edge may be a concern, but typically this direction has more resistance, limiting current and damping the effect of inductance (\$R^2 \gt \sqrt{L\,/\,C_\text{eff}}\$). After all, the transistor does nothing if we aren't using it to increase pull-down current from the driver; if it's not doing that, we might as well remove it, and put the driver there directly.

And if we need to boost both rising and falling edges, we should consider using a complementary emitter follower, or just a more powerful driver in general. (BJTs are often chosen as a handy cost-saving measure, especially when asymmetrical drive is required, so it's a common approach.)

The main downsides are the increased layout area and component cost, and the added VBE voltage drop, meaning the driver can't pull the gate all the way down, but ends a fraction of a volt short of GND.

Actually, this is a bit interesting in practice, because BJTs don't respond instantaneously, they stay "on" a little longer than the base voltage suggests they would. In terms of small-signal amplifier analysis, we find that an emitter follower has an inductive output characteristic; when loaded by a capacitance, its voltage gain actually increases slightly, particularly near the cutoff frequency (where the effective inductance resonates with the load capacitance, peaking the frequency response). Now, a gate driver is a pulsed circuit, far removed from the small-signal case, but a similar dynamic still applies, and the effect is, the transistor can stay on just a little longer, and pull the gate closer to the rail than otherwise expected.

This effect isn't easy to calculate, though; it depends on device fT, capacitances, drive impedance, load impedance, rate of change (dV/dt and dI/dt), etc. Suffice it to say, it's easier to measure a particular case. (Fortunately, gate charge doesn't vary wildly with switching conditions, so this is a reliable way to assess performance.)

In any case, whether the VBE drop manifests fully or not, it isn't a concern for higher voltage types where VGS(th) is many times VBE. This method can be questionable for low voltage and logic-level types, where VGS(th) can be 0.8V or even less, and the risk of an added VBE would absolutely break the design. (Low voltage, powerful, and fast, drivers are abundant, and would be an excellent choice for such an application.)

As for excessive source/emitter inductance (precisely, excessive inductance in common between drain/collector and gate loops), I have two rebuttals:

  1. Categorical: if this inductance is high, it's a bad design and the layout needs to be addressed. What effect it has on the gate driver, or any particular realization of one, isn't important.
  2. As long as it's not oscillating, or other extenuating circumstances, the main effect of this inductance is simply to slow down switching. Two reasons: (a) the in-place voltage drop acts to shift Miller plateau up during rise and down during fall; the limiting case is where it's depressed all the way to zero, and the gate driver simply can't drive the transistor any faster no matter how hard it tries -- the transistor is limiting its IG by way of V = LS dID/dt and that's simply what rate of change it will switch at; (b) any induction into the gate loop, or higher up in the driver-BJT loop, has a similar effect, because the BJT has unity gain and any induced voltage here simply serves the same purpose.

There could be extenuating circumstances where oscillation occurs, and these reasons no longer apply, or they become compounded by the circumstances; but again those will largely be solved categorically: if you're designing a pathological gate driver, don't be surprised if it has pathological behavior, right?... Avoid making oscillation loops, like connecting external capacitances between D/C and G, and G and S/E (this includes CJ of a zener diode or TVS if you opt to add voltage protection to it!); or if you must, dampen them with resistance, which can also be used to better define the Z, gm, etc. you are targeting by adding such components.

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