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I read this application note from Fairchild Semiconductors, and was wondering about what the possible disadvantages could be if a PNP transistor is used to bypass the Miller current as shown in the application note.

Would the increase of stray loop inductance be a possible problem since a PNP transistor will need some space to be put on the board, and that means the gate driver IC would be a bit further away from the main IGBT or MOSFET?

EDIT 1:- This is the part from the document I was asking about:-

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    \$\begingroup\$ Would the increase of stray loop inductance be a possible problem Everything's possible and everything can be a problem. So what to do? Quantify it, that means, put some numbers on the issue and do calculations and/or simulations to prove that it is a problem or not. A track of 1mm has about 1 nH of inductance so you could make a guess what the inductance will be. Then simulate that and see if the inductance matters (make the inductance zero and compare that to a more realistic value). The faster you switch the more of an issue any inductance is going to be. \$\endgroup\$
    – Bimpelrekkie
    Jan 24, 2021 at 18:50
  • \$\begingroup\$ @Bimpelrekkie, Ah yes, so I have heard the comment: "Talk is cheap, show me the numbers". Cheers \$\endgroup\$
    – tlfong01
    Jan 25, 2021 at 0:22

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The faster switching might cause problems with the existing inductance in the source, dragging Vo below ground through Rg and killing the driver chip.

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