# Why is the output of a high-pass filter not 0 when the input is 0?

I'm trying to design a 5th order Butterworth high-pass filter built on the Sallen-key topology with a cut-off frequency at 100Hz. For some reason, the output has a DC offset of around 5mV when the frequency of the input is less than the cut-off frequency even when the input is grounded.

I am using the Op-Amp LT1498 on LTspice and all the capacitor values through all three stages (first order, second order, second order) are 100nF. I'm guessing that its from the output of the op-amp but I'm not really sure.

The output is as follows from a 10Hz input:

Any help would be appreciated!

• what's the input offset voltage of that opamp?
– user16324
Commented Jan 25, 2021 at 19:48
• Try simulating with an ideal op amp to see if the offset goes away Commented Jan 25, 2021 at 19:54
• Post a schematic. What are the voltage rails? +/- or just positive and ground? The opamp might be "rail to rail" but the output will never be all the way to the rail. Look up the specification in the datasheet. Commented Jan 25, 2021 at 19:54
• @BrianDrummond typical 350uV, max 1300uV. I have edited the question to include the datasheet. Commented Jan 25, 2021 at 19:56
• @ScottSeidman I tried it with an ideal op-amp and it got rid of the offset. What parameter in the datasheet would that offset link to? Commented Jan 25, 2021 at 20:06

This could arise as the sum of the input offset voltages ... but for 3 opamps, that would only come to 3.9mV worst case, so that isn't it, especially since it's unlikely that the SPICE model has the worst case offset voltage.

But the opamp has a pretty large input bias current ... 0.65 uA.

Have you balanced the impedances on both inputs to the opamp?

If you fed one input from 10K source impedance and connected the other input to GND, (or fed it from a 0 ohm source) that input bias current would develop 6.5mV on one input, and 0 on the other.

The classic solution is to feed the other input from the same impedance, 10kilohms, so that both inputs are offset by the same voltage, which then cancels out.

simulate this circuit – Schematic created using CircuitLab

Easy to test this in your simulation.

(There is typically some mismatch between the bias currents on each input : this is called input offset current, and it's 10% or 65 nA for this opamp. So don't expect perfect cancellation, but you should be able to get much better than 5 mV)

The other approach, of course, (if the filter is driving a suitably high impedance load) is to implement the 1st order section as a passive RC filter on the output of a 4th order active filter. Then the C means the internal DC offsets don't matter...

Get rid of most of the capacitors in that filter, leave only small (10-100pF) ones across the negative feedback resistors. You'll see a similar 4mV output, I bet, so this has nothing to do with the filter. The filter is a red herring. Now, you may not like that 4mV offset, but that's a DC problem, so it will need to be solved like such DC problems are solved :) Sometimes a good solution to a DC problem is to ignore it by design. You have a high-pass filter, so why does the downstream circuitry care about there being DC offset? It probably shouldn't care. Of course it may be that you're only asking to understand it, and not because it's a problem in the circuit. Easy enough: solve the circuit for a DC operating point (you can do that manually with paper and pencil): use the open loop gain of the op-amp from the datasheet, as well as its maximum input offset voltage, and also input bias and offset currents.