# Designing Schmitt trigger oscillator using CMOS NAND gate

I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um technology.

Question: it can be seen in the result, the charging time of the capacitor is large which affects the oscillating signal at the beginning. To reduce charging time I need to reduce the RC time constant but it affects my oscillating frequency. Once I reduce the RC time constant then I am limited to a certain oscillating frequency.

Oscillating frequency: f=1/2.2RC

How can I reduce the charging time of the cap (other than the RC time constant in my schematics) so that I get the least distortion at the initial stage of the oscillating signal?

Two possible solutions:

1. Reference the cap to Vcc/2. A resistor divider will waste power, but is simple. R1 must be large compared to R2 & R3.

2. Divide the oscillator down by 8 or 16 or more. Then the first unequal period will have a much smaller effect on the output.

simulate this circuit – Schematic created using CircuitLab

• Thanks for your proposed solution. I need to integrate the circuit so voltage divider or Binary divider would affect power consumption and we also have space constrain on the IC chip. Commented Jan 27, 2021 at 9:57
• @Bam_Khel Note that this works with a capacitor divider too, saving bias current. If you have enough metal layers, I suppose it doesn't cost any extra space, either. Commented Jul 19, 2022 at 6:30

simulate this circuit – Schematic created using CircuitLab

What you wanted is on the right.

Note how in the circuit on the right the voltage across the capacitor C2 goes directly into the input of the Schmitt trigger.

Now what happens is that the NAND1 is detecting the charging of the capacitor. That means the voltage across the capacitor will only vary a little bit as the 0 / 1 detection window of a NAND is small, just like an inverter. Slightly above Vdd/2 = 1, slightly below Vdd /2 = 0.

You actually want these levels to be higher and lower so that the C0 charges / discharges to about 1/3 Vdd and 2/3 Vcc and that's what a Schmitt trigger can do.

But that Schmitt trigger is after the NAND, which outputs 0 or 1. Therefore your Schmitt trigger isn't doing anything useful!

So move the Schmitt trigger like I suggested and try again.

If you want to build a real Schmitt trigger NAND gate, use this schematic:

Found here.

• "What you made in your schematic is this (left):" That's just not true. A Schmitt trigger NAND gate responds as a Schmitt Trigger on both inputs, Note that both NAND gates in the OPs schematic are Schmitt Triggers. Commented Jan 26, 2021 at 22:20
• @WhatRoughBeast A Schmitt trigger NAND gate responds as a Schmitt Trigger on both inputs I agree, however the NAND gate that OP has drawn is a standard one. Please look at the Cadence schematic and see how OP's schematic is not a Schmitt trigger NAND. "What you made in your schematic is this (left):" That's just not true It is if I translate the Cadence schematic back to a functional block diagram. Commented Jan 27, 2021 at 7:56
• @WhatRoughBeast I added the internal schematic of a real Schmitt trigger NAND gate, compare it to the NAND gate that OP was using and notice how OP's NAND does not have the two extra MOSFETs that are needed for the positive feedback. Commented Jan 27, 2021 at 8:43
• @Bimpelrekkie Thanks for your proposed solutions. I tried the schematics on the right side and it works fine for my project. Commented Jan 27, 2021 at 10:46

Any reason why you can't leave the oscillator running, and just gate it at the output?

simulate this circuit – Schematic created using CircuitLab