Creating a new project in Vivado and importing the core openMSP430 (https://github.com/olgirard/openmsp430) files, I could easily test everything out by setting tb_openmsp430.v as the top file in the simulation and by using the pmem.mem file generated by compiling "core/sim/rtl_sim/src-c/sandbox". I have created my own modules "tb_openMSP430_fpga.v" and "openMSP430_fpga.v" in order to simulate and later synthesize the project for an fpga.
// *File Name: tb_openMSP430_fpga.v https://pastebin.com/xvtdBz9R
And for synthesizing:
// *File Name: openMSP430_fpga.v https://pastebin.com/PrcTpF6S
tb_openMSP430_fpga.v as the top file and trying to simulate the project does not seem to produce meaningful output and the register values remain the always the same during the simulation.
What is my mistake in the two
_fpga.v files that I created (in practice altered from the existing ones that Oliver created)?