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(Beginner here!): I am building a circuit where I am using an AND gate with some input voltages. If the gate output is high for a given (continuous) amount of time, I want to trigger another circuit. The delay length is 0.5s.

So if AND gate signal persists for 0.5s, then the next portion is triggered. I wanted to use something like the 555 timer, but I'm not sure if this is the right approach (I need the timer to reset if the signal ends before the 0.5s cutoff). Is using the 555 timer the right track? If it is, how should I pick the right combination of other components to get this desired time interval?

Again, I am a beginner so I do apologize if this isn't very technically sound/informative. Any help is appreciated.

EDIT 1: RC Circuit Based Attempt with Buffer:

enter image description here

EDIT2: RC Circuit Based Attempt with Buffer and Schmidt Input enter image description here

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  • \$\begingroup\$ I'd use a different diode than the ancient 1N4148 (some Schottky diode), other than that, looks fine. Also, C1 is maybe 2 or 3 orders of magnitude larger than I'd recommend. \$\endgroup\$ Commented Jan 27, 2021 at 23:26

3 Answers 3

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A 555 would certainly be a viable component to realize this!

However, it would also be a bit of a complex solution, if your accuracy requirements are low.

Assuming the circuit you want to trigger is also a logic gate with a well-defined low-high threshold that you can rely on, it would be much easier to charge a capacitor with your AND's output slowly (when high) and discharge it quickly (when low). Something like:

                D        Some other circuit's input
   -----   ----|<----
--|     \  |        |     |\
  | AND |--·-====---·-----| >
--|     /      R    |     |/ 
   -----            = C
                    |
                    V GND

What happens here is that the output of your AND gate charges the (let's assume) previously uncharged C through R. R limits the current very much, and thus takes time; assuming R is high enough (e.g. 100kΩ) to never "significantly" load the AND gate's output, we can model the gate output as a constant voltage source, and that means the voltage across C follows an \$U(t)=U_{max}·(1-e^{\tau t})\$ function, ie. it's nice and monotonously growing. You can control \$\tau\$ through choice of R and C.

At some point, the threshold voltage of your "other triggered circuitry" is reached. If you tuned this correctly, that's after 0.5s (do use an adjustable resistor - it makes fine-tuning easy).

This charging happens for as long as the output voltage of your AND is higher than the voltage over C.
If, however, the AND toggles its output and becomes lower than the voltage over C, then D is not in reverse bias anymore - it starts conducting, and quickly so, thus discharging C relatively rapidly. (Hence, use a large R and a low C value, if possible, as that discharge current could else fry your AND gate. Also, use a Schottky diode as D - they have low forward voltage.)

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  • \$\begingroup\$ That is quite helpful, so my choice of R and C alone should be sufficient in setting the timer. My triggered circuitry is simply an LED that will light up, and I need the system to latch so that only a power reset can unlight the LED. In this case, what should I use "after" the output. Should I use a relay here? \$\endgroup\$
    – EENoob
    Commented Jan 27, 2021 at 22:45
  • \$\begingroup\$ I guess I can also maybe use a comparator? \$\endgroup\$
    – EENoob
    Commented Jan 27, 2021 at 22:47
  • \$\begingroup\$ definitely not a relay – a relay uses a lot of current, and you need that current to be "basically 0". So, a series of two NOTs, or an OR with the other input to ground, or an AND with the other input to VCC, or just a buffer. \$\endgroup\$ Commented Jan 27, 2021 at 23:04
  • \$\begingroup\$ A comparator works, well even, but you need to generate some voltage to compare to. So, that would be a job for another two resistors to form a voltage divider. \$\endgroup\$ Commented Jan 27, 2021 at 23:05
  • \$\begingroup\$ I have made an edit to my original post trying to implement the above, along with the buffer. If I have done this correctly, is it now the case that the output of the buffer is high only when the time limit is reached? I am not sure how to get an estimate for the time scale using my values for RC. \$\endgroup\$
    – EENoob
    Commented Jan 27, 2021 at 23:14
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Trying to achieve such long delays (e.g. 0.5s) with R-C is fraught with issues. This is even a bad idea with a 555, which at least has some snap-action (hysteresis) but still isn't that reliable.

Instead, for a long time interval like that consider using a counter like the CD4060. The CD4060 includes its own R-C oscillator for the timebase; it can also use a crystal for even greater accuracy. It has active-high reset. Combined with some CMOS logic, you can make a delay that can detect your condition, count up, then stop until the condition is cleared.

Examples of CD4060-based counters are plentiful, it's very popular for cheap industrial timers.

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The EDIT 1 circuit will work fine with one important change. BUF1 must be something with a Schmitt trigger input. Without it, the BUF1 output will be a noise burst as the very slow input voltage ramp crosses the gate's transition region, where it is basically a high gain amplifier. Random noise on the input will appear as a burst of very narrow square waves at the output.

Most Schmitt gates are inverting. If this change in logic polarity is a problem, you can fix that by changing the AND gate to a NAND gate are reversing the diode. Or, grow your own non-inverting Schmitt stage with two buffers and two resistors.

UPDATE:

First - to use an opamp in this logic circuit, it must be powered by the same 0 V and 5 V that the logic is so that the output voltage swing is compatible with the downstream circuit's input. That is a problem later.

To use an opamp as a Schmitt trigger stage, the input parameters are determined by the output parameters of whatever is driving it. Assuming AND1 is a CMOS gate, it has a pretty much rail-to-rail output so the midpoint of its output signal is 2.5 V. To make the Schmitt input transition levels (there are two of them) symmetrical about this, you start with a 2:1 voltage divider between the rails (R14 and R15), and then add hysteresis to that (R16). At 5 V, the two transition levels have to be only about 0.5 V apart, or 10%.

For example, if R14 and R15 are 10 K, that is a 5 K impedance at the centerpoint. 9x that is 45K, so setting R16 to 47K will yield approx. +/-0.25 V for the two transition levels.

That's all great if the opamp has rail-to-rail inputs and outputs, but the TL08x does not. If you need to stay with that part, then the calculations get a bit messier. And, the input stage characteristics might rule out this part.

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  • \$\begingroup\$ So if I am understanding this correctly, I should put a Schmitt trigger in between the buffer and the timer portion? \$\endgroup\$
    – EENoob
    Commented Jan 28, 2021 at 0:41
  • \$\begingroup\$ The Schmitt-input device should be connected to the R12-C1 node. \$\endgroup\$
    – AnalogKid
    Commented Jan 28, 2021 at 1:04
  • \$\begingroup\$ I've just made an edit with the Schmidt-input, would appreciate it greatly if you had any feedback. I used this website to get the resistor values: hyperphysics.phy-astr.gsu.edu/hbase/Electronic/schmitt.html#c2 I'm not sure if I have set the trigger voltage cutoff and bottom threshold correctly, though. \$\endgroup\$
    – EENoob
    Commented Jan 28, 2021 at 1:06
  • \$\begingroup\$ See updated answer. \$\endgroup\$
    – AnalogKid
    Commented Jan 28, 2021 at 4:30
  • \$\begingroup\$ I don't need to stay with the part, do you have any recommendations for which one I could use instead? \$\endgroup\$
    – EENoob
    Commented Jan 28, 2021 at 16:37

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