- how exactly does glitch happen for rising-edge and falling-edge ICG ?
- Why for the top version of rising-edge ICG, there is no X at the MSB of the latch output ?
Note: TE signal is asynchronous to CLK, and see also the red 0 and 1 at the output
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The issue stems from the fact that in the first case, gating the clock causes it to go high, but in the second case, gating the clock causes it to go low.
To illustrate the problem, consider the situation where the fourth clock gate circuit is used but the clock gate signal is registered in the riding edge. In this case, the clock gate register output changes right after the clock goes high. Since the fourth circuit is used, the gate causes the output clock to go low, causing the clock to return low almost immediately after it became high.
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\$\begingroup\$ I do not understand what you meant by "Since the fourth circuit is used, the gate causes the output clock to go low, causing the clock to return low almost immediately after it became high.". Besides, how does your explanation actually lead to glitch ? \$\endgroup\$ Jan 28, 2021 at 9:02
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\$\begingroup\$ Why out of the 4 circuits above, only 2 circuits have glitch ? \$\endgroup\$ Jan 30, 2021 at 1:30