Yes, it can be done, but you may need to slightly enlarge your 0402 cap pads to ensure the hole in the middle doesn’t take up all of the exposed pad area.
However, I recommend a different approach. Depending on your requirements, you could try putting the caps on the same side of the board as the FPGA. This isn’t always ideal but it can be made to work for many applications, and can even be superior to caps on the back in some cases.
What you need to do is approximate the inductance between your FPGA’s power and ground pins with caps on either the front or back. If you can design your layout such that the inductance with caps on the front is not too much greater than with caps on the back, then your board will work unless your system is approaching the limits of SSO noise, etc.
But how do you estimate this inductance? Inductance in a circuit is proportional to the area enclosed by that circuit. In your application, the circuit is between the FPGA Vcc, cap Vcc, cap GND, and FPGA GND. Here is a visualization of the inductance estimation (courtesy EDN):
Do this estimation for the case where you have caps on the front and caps on the back. If you can minimize the area enclosed, then your system will likely work. Consider using additional closely-spaced power and ground planes to minimize the inductance. Indeed, if using very closely-spaced power and ground planes which are close to the component side of the board, it is possible to achieve lower inductance with caps on the front than on the back.