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I have taken this from the FGPA XIlinx documentation, it says that a single 6 input LUT can be configured to be 2 5 input LUTs. Does anyone know how this is implemented?

Does a single address signal essentially enabled different LUT masks or memory?

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  • \$\begingroup\$ I don't understand the question – The paragraph you cite seems to describe what is done pretty exactly. \$\endgroup\$ Jan 28, 2021 at 17:27

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They are made from a 5 input, 2 output LUT (32x2) followed by a bypassable mux. The mux takes the 6th input to select one of the two outputs.

The thing to keep in mind is that it isn't really two 5-input LUTs, it's a 5-input, two-output LUT. Or you can think of it as two 5-input LUTs that share the same inputs. The synthesizer can pack two different logic functions into a 5-input, 2-output LUT so long as the number of unique inputs is 5 or less - so you could have 3 unique inputs on one and 2 on the other, or 2 unique inputs on both plus one shared input, etc.

Figure from the Spartan-6 CLB user guide (UG384):

Spartan-6 LUT6

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  • \$\begingroup\$ Why cant you use the some of the inputs as selectors? For example, 5input LUT has 32 memory cells. Which is enough to implement 2 4-input boolean functions. Using the 5 inputs 1 bit acts as the selector bit for which 4-input boolean function \$\endgroup\$
    – Yogi Bear
    Jan 29, 2021 at 18:41
  • \$\begingroup\$ You can fit two four input logic functions that share the same inputs as well as a mux into a single 5 input logic function, and then put that on one LUT without the need for any extra components. \$\endgroup\$ Jan 29, 2021 at 20:02
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The LUT has 64 cells and can be configured in either of two ways.

When used as a 6 input LUT with 1 output it is configured as 64x1.

When used as a 5 input LUT with 2 outputs it is configured as 32x2.

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  • \$\begingroup\$ Ahh okayy thanks \$\endgroup\$
    – Yogi Bear
    Jan 28, 2021 at 17:57

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