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Im not sure in how the Distributed RAM is implemented using LUTs. Would the inputs be used for both address, control write/read and data signals?

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    \$\begingroup\$ The logic block is either configured as ram OR a LUT. \$\endgroup\$ – Kartman Jan 29 at 14:57
  • \$\begingroup\$ Depends on the FPGA mfg and device family. For most newish Xilinx parts, see Kartman's comment. Or your FPGA's documentation. \$\endgroup\$ – user_1818839 Jan 29 at 15:55
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A LUT is a dual-port SRAM. It has a read port (address in, data out), which is how you use it for logic. But it also has a write port (address in, write enable in, data in), which is how the FPGA's start-up logic transfers data from the nonvolatile configuration memory into the SRAM following power-up.

It just takes one more configuration bit to make the LUT usable as distributed RAM, and that bit controls a multiplexer for the write port. That multiplexer's second input is available to the user logic, so now you can both write to and read from the SRAM.

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  • \$\begingroup\$ Thanks but how can you use a 6input LUT as Distributed RAM? Are the inputs broken into data signals and control signasl? \$\endgroup\$ – Yogi Bear Jan 29 at 22:50
  • \$\begingroup\$ The original 6 inputs are the address bus for the read port. There are additional inputs for the write port (6 address, 1 data in, 1 write enable) that become available when the mux is activated. \$\endgroup\$ – Dave Tweed Jan 30 at 11:36
  • \$\begingroup\$ Got it thank you \$\endgroup\$ – Yogi Bear Jan 30 at 15:43
  • \$\begingroup\$ @YogiBear I think it would be appropriate to accept Dave's answer if it answered your question! \$\endgroup\$ – Marcus Müller Mar 10 at 16:43

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