Im not sure in how the Distributed RAM is implemented using LUTs. Would the inputs be used for both address, control write/read and data signals?
A LUT is a dual-port SRAM. It has a read port (address in, data out), which is how you use it for logic. But it also has a write port (address in, write enable in, data in), which is how the FPGA's start-up logic transfers data from the nonvolatile configuration memory into the SRAM following power-up.
It just takes one more configuration bit to make the LUT usable as distributed RAM, and that bit controls a multiplexer for the write port. That multiplexer's second input is available to the user logic, so now you can both write to and read from the SRAM.