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The circuit diagram for the LED driver in this datasheet shows the shift register latch and clock being wired together. Will this work? I would assume so since TI has it in their datasheet. However, the description for the SCLK pin says that "A rising edge on SCLK is allowed 100ns after a rising edge of LAT". If that's the case how is it okay to wire the latch and clock pins together?

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The circuit diagram for the LED driver in this datasheet shows the shift register latch and clock being wired together.

It looks that way at first. But look at the /3 on the connection between IC1 and ICn. That means it is a 3 wire bus, not a single wire.

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Will this work?

No, because:

A rising edge on SCLK is allowed 100ns after a rising edge of LAT

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  • \$\begingroup\$ Ah, I was unaware that /3 was the notation for a 3 wire bus. Thanks for clearing that up! \$\endgroup\$ – transmogrifier Jan 31 at 5:31

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