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So I'm studying MOS transistors and came across the topic of capacitances between various terminals/contacts, including the bulk terminal. These capacitances are due to lateral diffusion as a consequence of the self-aligned process of the MOS transistors, the channel charge and the PN junctions formed in the MOS. Anyway, a capacitance value that is never defined is the capacitance between the nwell and the p-substrate in a PMOS transistor. These capacitance is never modelled in the schematic, unless we can extract it from the layout of the transistor. Can someone explain me why?

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In general, the nwell and p-substrate (or pwell and n-substrate) will be connected to ground and to the power supply voltage. (I am assuming that we are talking about conventional CMOS logic circuits here.)

Since both ground and the power supply voltage are assumed to be d.c. there will be no current flow between a well and a substrate. In other words, this capacitance has no effect.

Of course this a model of reality and it may not be the most appropriate model if you are changing the voltages of the wells, or if you are relying on the well/substrate capacitance for some reason. However, for typical CMOS logic design this model is the most useful model.

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