# Capacitances in a PMOS transistor: what about the n-well?

So I'm studying MOS transistors and came across the topic of capacitances between various terminals/contacts, including the bulk terminal. These capacitances are due to lateral diffusion as a consequence of the self-aligned process of the MOS transistors, the channel charge and the PN junctions formed in the MOS. Anyway, a capacitance value that is never defined is the capacitance between the nwell and the p-substrate in a PMOS transistor. These capacitance is never modelled in the schematic, unless we can extract it from the layout of the transistor. Can someone explain me why?