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So I have a proprietary system that outputs high when there is an error, and low when there's not.

I want to put this signal onto a D flip-flop clock, so that if theres an error, my system clocks a high signal out, which latches the system off.

The D flip-flop clocks on rising edges, so in order to always catch an error I want to turn the high signal from the proprietary system into a pulsing signal.

I am open to suggestions, but this is some of the ideas I have, and the questions I have regarding them.

  1. Run the error signal into a AND gate together with a oscillator.
  2. Run the error signal into the enable pin on a oscillator. However, I'm a bit uncertain what happens when the clock is disabled. Can I have a pull-down on the oscillator output?

I've added a circuit showing the D flip-flop, however, it also has a clear pin, which I use at start up to make sure things start up correctly.

schematic

simulate this circuit – Schematic created using CircuitLab

So the error signals latches the system in an error-state, i.e. it clocks the 3V3 onto the output, theres no way it can change without restarting the entire system.

Oh, and cost is less of an issue than many components/complexity.

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    \$\begingroup\$ Your error signal needs to go into the D input and, when you need to update the flip-flop output, you apply a clock pulse to CLK. Anyway, that's how I read what you want. \$\endgroup\$
    – Andy aka
    Commented Feb 3, 2021 at 11:00
  • \$\begingroup\$ I suppose it's a bit unclear from my description. But the idea is that when the error signals, it latches the system in an error state. So if I clock the 3V3 onto the output, theres no way I can change that without restarting the entire system. \$\endgroup\$
    – Viktor
    Commented Feb 3, 2021 at 11:05
  • \$\begingroup\$ OK, that makes more sense. \$\endgroup\$
    – Andy aka
    Commented Feb 3, 2021 at 11:05
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    \$\begingroup\$ You need to use an RS flip flop instead (R: Reset, S: Set). Wire the error signal to the "set" input and it will behave as you want. Then use the "reset" input to reset it when desired.. \$\endgroup\$
    – user173292
    Commented Feb 3, 2021 at 11:08
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    \$\begingroup\$ No neither would "win" it would cause an undefined state, but you can prevent that using an and-gate with a single inverted input... There are also lots of other ways to accomplish this, but the solution I show in my answer is simple and works.. \$\endgroup\$
    – user173292
    Commented Feb 3, 2021 at 11:27

1 Answer 1

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Use an RS flip-flop instead.

schematic

To prevent the flip-flop from unintentionally being reset while the error is still present use an and-gate with one inverted input, as shown above.

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