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I am doing a simple NMOS simulation where my W/L ratio was set to 20. I then increased the width and length of the MOSFET, however the overall W/L ratio was still 20. One thing I noticed was the drain current decreased. Shouldn't the larger W and L increase the current?

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Your SPICE model might calculate an effective channel length by subtracting a small amount from the specified (drawn) value, to account for diffusion of the source and drain implants under the gate. Since this is a fixed distance it has a much larger effect when the drawn length is small, increasing the effective W/L when L is small. Of course, without analyzing the actual model we can't be sure.

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  • \$\begingroup\$ Barring any unforeseen simulation specifics, is there any fundamental reason the drain current would decrease? Could it be due to the channel length modulation and increased resistance? My MOSFET has a gate voltage of 1V, source voltage of 0V and drain voltage which linearly increases from 0 to 5V. \$\endgroup\$ – PrematureCorn Feb 7 at 19:28
  • \$\begingroup\$ is there any fundamental reason the drain current would decrease? Yes your "small" MOSFET suffers more from 2nd order effects (like channel length modulation) compared to the "more ideal" larger MOSFET. \$\endgroup\$ – Bimpelrekkie Feb 7 at 19:36
  • \$\begingroup\$ @Bimpelrekkie Then why did my MOSFET with a larger area have a smaller current which leads to larger channel length modulation value? \$\endgroup\$ – PrematureCorn Feb 7 at 19:45
  • \$\begingroup\$ No, a larger MOSFET gives a smaller influence of the channel length modulation. 0.5 \$\mu\$m => 0.4 \$\mu\$m is a 20% decrease, 4 \$\mu\$m => 3.9 \$\mu\$m is a 2.5% decrease. The amount that the channel size decreases is the same: 0.1 \$\mu\$m for each case. A 0.1 \$\mu\$m decrease has a larger influence on 0.5 \$\mu\$m compared to 4 \$\mu\$m. \$\endgroup\$ – Bimpelrekkie Feb 7 at 20:49
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If you started with a 20/05 NMOS and your \$V_{DS}\$ was large (more than 2 V for example) your NMOS would experience channel length modulation which decreases the effective channel length. Your effective gate length could for example be decreased by 0.1 \$\mu\$m making it 0.4\$\mu\$m (instead of 0.5 \$\mu\$m). That smaller gate length then increases \$I_D\$.

When you "scale up" that NMOS to for example 80/4, apply the same \$V_{DS}\$ you would again suffer from channel length modulation but the result on the effective would be much smaller: 4 \$\mu\$m - 0.1 \$\mu\$m = 3.9 \$\mu\$m. This change is much smaller! So the increase of \$I_D\$ will also be much smaller.

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  • \$\begingroup\$ I understand what you mean but my original MOSFET had a W/L = 12/0.6 then I changed it to 24/1.2 and my drain current decreased. Therefore the decrease in current actually increased the channel length modulation since they are inversely related \$\endgroup\$ – PrematureCorn Feb 7 at 20:55
  • \$\begingroup\$ Again no, you don't seem to understand channel length modulation properly so go read the Wikipedia page carefully. Then make two sideview drawings of your 0.6 \$\mu\$m and 1.2 \$\mu\$m channels and include the depletion layer around the drain. Forget about "inverse relations" in formulas, first understand what happens physically only after that understanding do the formulas start to make sense. There are also several videos on Youtube explaining channel length modulation. \$\endgroup\$ – Bimpelrekkie Feb 7 at 21:19
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Increasing both width and length of a transistor by the same factor will not increase the overall W/L ratio. However, the length of the device is proportional to the early voltage (VA). In other words, if the length is doubled, the early voltage will also be doubled. This will cause the drain current to decrease by a factor of 2 and the transistor's output resistance ro = VA/IX increases by 4 times. The 4x increase comes from the 2 times increase in VA and 2 times decrease in IX or drain current.

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