I have a design with chained modules. Each of them is a pipelined design, so the output in each of them take more than 1 clock cycle. To perform the test bench, I have created so many registered signals as stages in the pipelined designs to delay my gold test and compare it with the real output. An example:
// If module 1 has 4 stages: reg [31:0] G1, G2, G3, G4; always @(posedge CLK) begin G2 <= G1; G3 <= G2; // This is the the gold test bench synchronyzed // with the output from the pipelined module G4 <= G3; end
In this way, I can compare the output of my module with the gold test. Other way is using time delays:
always #50 GOLD = output_from_module;
What is the best way to check an output that is delayed more than one clock cycle?