I'm wrapping my head around this layout, I'm trying to extract its schematics so I can determine the logic function. enter image description here

For what I understand we have two PMOS and two NMOS transistor. I see one connection to VDD, then a common diffusion and a connection to the output (yz). So the PMOS transistors are in series. However the same seems to happen in the bottom NMOS transistors. How does this happen? Shouldn't the two top transistors be in series and the bottom in parallel and vice-versa. I also don't quite understand what are "s", "sz", "y", "yz". I suspect this might have something due to logic negated inputs/outputs but I don't quite understand how does that translate in a schematics. I suspect this translates a logic function that is not as simple as I might be thinking. Can someone help me?

  • \$\begingroup\$ Shouldn't the two top transistors be in series... Why should they? You can only conclude that they need to be in series after you've seen the schematic. How about simply drawing in NMOSs and PMOSs on top of this picture and drawing the connections. Then what do you get? You're confusing yourself as you're trying to recognize certain structures that aren't there. So "act stupid", simply draw the components and the connections. Then you can draw a schematic. You might have to re-draw that schematic a few times to have it make sense. \$\endgroup\$ Commented Feb 7, 2021 at 21:33
  • \$\begingroup\$ Oh and the circuit isn't a standard inverter but a "special" inverter with extra inputs. How do I know? I simply follow the connections between the components. I do have plenty of layout experience so that helps ;-) \$\endgroup\$ Commented Feb 7, 2021 at 21:36
  • \$\begingroup\$ @Bimpelrekkie how I think I get it now? It is a tri-state inverter right? Input y, output yz, s and sz are the enable signals, right? \$\endgroup\$ Commented Feb 7, 2021 at 22:05

1 Answer 1


I believe this is a layout for a tri-state buffer. In this circuit, both the top two PMOS transistors are in series as well as the bottom two NMOS. The middle two MOSFETs are used to turn the tri-state "ON" or "OFF" and then the outer two MOSFETs act as a normal buffer/inverter. The "z" labels seem to suggest the inverted of the normal signal.

enter image description here

Image source: https://www-inst.eecs.berkeley.edu/~cs150/sp11/agenda/lec/lec08-cmos.pdf


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