I want to use a DDR3 RAM in conjunction with a FPGA. The FPGA will control the DDR3 RAM. I am using a XILINX 7series FPGA. XILINX has a guide for this, on p.129 is the needed termination mentioned, this can also be seen in below image.
Point 3 states that unidirectional signals need a 40Ohm VTT termination. And bidirectional signals need the termination at both ends. I have a DDR3 memory with an option for a on die termination. So when I use this on die termination do I still need the VTT termination?
The DQ Pins (data) are bidirectional so I will need a termination at both ends. All other pins are unidirectional, right? So they will just need a termination at the receiver side.