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I have a technical question asking how to use this IC in my application.

I am converting 0 to 5Vdc from a potentiometer to a 12-bit digital representation using a 12-bit parallel output ADC IC. This IC is an LTC1273BCN. :I have attached the datasheet in this link.

I am reading these 12 bits with 12 digital inputs on a FPGA. The IC is powered with 5Vdc.

But I don't understand some pin connections on the IC. Below is my understanding of the IC:

Pin 24: +5Vdc supply

Pin 23: Ground

Pin 1: Analog input from potentiometer

Pin 3: Ground from potentiometer supply

Pins 4-11 and 13-16: ADC output 12-bits

What are the rest of the pins used for (pins 2, 19, 20, 21 and 22)?

How are these used in the ADC process? I would like the ADC chip to continuously convert the analog output without being told to do so by the FPGA. Or is this how the IC is designed to function?

Thanks

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    \$\begingroup\$ Ah let me see. Pin Functions (Page 8 of datasheet) 02 = Vref Output, 19 = HBEN (High Byte Enable), 20 = ~RD (Read = starts conversion), 21 = ~CS (Chip select), 22 = ~Busy (Low when conversion in progress). Cheers. \$\endgroup\$
    – tlfong01
    Feb 8, 2021 at 9:53

1 Answer 1

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Well, the function of the other pins is explained from page 15 of the datasheets, they are mostly used for adapting the converter to various kind of buses. Choose the one you like better and program the FPGA accordingly, in the following pages there are diagrams for the supported bus cycles.

As an aside: you noticed that this is a 5V part, right? there aren't many FPGAs around which handle these, you'll probably need level shifters.

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  • \$\begingroup\$ Thanks for your reply, I have used opto-couplers to isolate and convert the 5V to 3.3V. I have read the datasheet but do I need to use the FPGA to initiate the ADC conversion? Can I tie pins 20 and 21 low, and will the ADC chip continuously read the input and convert it? \$\endgroup\$
    – David777
    Feb 9, 2021 at 9:51
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    \$\begingroup\$ You really need optos? I suppose this is working on a different power rail then. Many ADC support a continuos conversion mode, more or less like you said. This part need a start conversion (tied more or less to the /CS), the only option you have is to wait for the result or read the previous already completed one. If you are using optos and have an FPGA maybe it could be easier to use a serial output converter or even a sigma delta modulator to reduce the number of lines to pass thru isolation. From the same manufacturer, for example, the LTC2312-12 only needs 3 signals \$\endgroup\$
    – Lorenzo Marcantonio
    Feb 9, 2021 at 10:29

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