3
\$\begingroup\$

As you can see from my previous question, I am trying to measure resistance within the range of 200k-60 ohms (around 4-5 decades). I will be using a pulse (5us pulse width and 50ns each rise and fall time) voltage source of 200mV (max) across the RUT (resistor under test) and measuring the pulse current using a TransImpedance Amplifier (TIA).

Now I am planning for a programmable gain TIA and here is the below circuit.

enter image description here

I have chosen 4 approximate switchable gain of around 430, 4.3k, 43k, 430k that is good enough to measure the above-mentioned resistance range. In the circuit, I have used an ultra-low input bias current and low input capacitance opamp LTC6268 with ±2.5V supply followed by an inverting amplifier (LTC6228) with a gain of 3. The output of this opamp goes to a bipolar input ADC[AD7606C-18](hence inverting is not really needed but still I kept it for now) The switch is ADG613 (4 SPST switches) with low charge injection and low on/off source/drain capacitance (5pF each at Freq=1MHz).

There are 4 resistors connected to 4 switches. The voltage sources V8, V7, V6 are 3.3V digital pulses (more like digital steps, see point '1' below) to turn connect/disconnect the 430k resistor, 47k resistor, 4.7k resistor, and the 430 ohms resistor respectively. V9 is just a dummy here since the 430k resistor is always connected (the trigger is connected to the ground permanently). Now one may question the value of the resistors which are not the same as my gains. The reasons are:

  1. I'll be changing the gain by adding (using the switches) resistors in parallel by connecting them one after another (higher to lower) without disconnecting the previous one and taking the equivalent resistance (from the highest to the current lowest) and hence the equivalence gain. The voltage sources V8, V7, V6 act like digital step trigger for the switches activating them one after the other with a certain delay. Instead of switching one resistor on at a time, I saw that this approach reduces glitching a bit.
  2. Doing some trial and error in the simulation I found that when considering approach '1' and the internal resistance of the switch (which is modeled) the chosen set of resistors give a fairly decent approximation of the above-mentioned gains.

I'll be using 4 pulses for single resistance measurement and during those 4 pulses approach '1' would be used (i.e. connecting a new lower value resistor at each pulse to give a new equivalent gain), which would give me four different results and using software thresholds I can choose one of the 4 readings to get an accurate measurement.

Here are some results when trying different decades of RUT 60 ohms, 600, 6k, 60k, 600k in the respective order. V(n008) is the output (in green). V(n009) is the input pulse (in grey) and the rest (V8, V7, V6) are triggers of the switches. The output will be sampled only during the input pulses so glitches due to switching are not a real problem as long as they settle before the actual input pulse. Here is another set of results (switch trigger voltages are hidden) showing the glitches more clearly. The parameters are exactly the same as the previous result.

As you can see for smaller resistances the higher gains make the opamp reach saturation and therefore I have chosen a meaningful range of 4V and 0.4V for measurement in any decade to be valid (software threshold as mentioned before).


So all these look good in simulation but before putting it in the PCB, I want to know your opinion of the required changes and consideration required to achieve this simulation behavior as close as possible with actual non-ideal PCB. I mean things like adding capacitors across resistors as compensators (if required) to prevent ringing at the output, maybe some noise consideration, or some additional passive components for any other purpose.

I also understand that using 5 resistors would be ideal but I am okay with a small decrease in resolution around 200k resistance (a change of 1k results in 7mV change, which is still easily measurable) So I chose 4 resistors.

Edit: After adding parasitic capacitance of the switch (5pF each for source and drain), I was getting oscillation in my simulation for pulses when the lowest gain resistor was connected (when measuring higher RUT values). I know I won't be using that reading (I would be using readings from higher gain resistor for high RUT values) but if my opamp is not stable then it could cause my whole system to be unstable. I somehow fixed the issue by adding different decades of parallel capacitors across all the Feedback (gain) resistors as shown here (the pic also shows the parasitic switch capacitance). The values were chosen with trial and error. After this, the oscillation didn't occur. Is this the right way to do it? Would this work? Could someone explain what is happening here? How can I improve it?

\$\endgroup\$
0
4
\$\begingroup\$

A few observations: -

  • Have you considered worst case or typical leakage currents from the analogue switch? With 6 nA leakage current (worst case) through 200 kΩ there will be an error voltage of 1.2 mV at the input of U1 and that, on the highest gain configuration will mean an offset error voltage of about 108 mV on U1's output and three times this on U4's output.

  • You have focused only on choosing a really good low bias current op-amp for the front end but I think the ADG613 will be the dominant factor on bias currents.

  • What about on resistance - have you factored that into your resistor feedback network? It could add 100 Ω to the 430 Ω feedback resistor (FB1) and be an annoying error term.

  • Is the LTC6268 capable of driving a 50 ohm load (R6)?

  • Are the control lines for the analogue switch referenced to the negative rail? With a split rail (GND pin at 0 volts), the split supply must be not less than +/- 2.7 volts and your schematic shows +/- 2.5 volts for Vdd and Vss. You can overcome this by running in single rail mode but, GND must connect to -2.5 volts and your logic control lines must also be -2.5 volt referenced.

  • Don't forget supply decouple capacitors for the chips.

\$\endgroup\$
12
  • \$\begingroup\$ Thank you. I will be answering in the reverse order. 6) Yeah, I'll decouple the supplies. 5)The analog switch and the inverting amp are connected to ±5V (Vss2, Vdd2) and only the TIA is connected to ±2.5V(Vss, Vdd) so I think that is ok. 4) At saturation, through the LTC6268 and the 50ohm resistor what I see is a max current of 35mA, while the typical Output Short Circuit Current of LTC6268 is 80mA so that should also be alright. \$\endgroup\$ – paulplusx Feb 10 at 16:17
  • \$\begingroup\$ 3)Yes, the model I have used also models the internal resistance so accordingly I have chosen my resistors with some trial and error to replicate approx equivalent gains of 430k, 43k, 4.3k, and 430. I'll do some more trials to refine the values. 2)ADG613 has a very low source and drain capacitance (5pF) and low charge injection (1pA) so I picked it, couldn't find any other switch with lower parasitic capacitance. \$\endgroup\$ – paulplusx Feb 10 at 16:19
  • 1
    \$\begingroup\$ Adding the capacitors is a bona fide fix (see this question I recently answered). In effect, you are making the op-amp gain fall below unity before the unwanted phase change reaches 180 degrees. It can't oscillate if the gain is less than unity and, it can be a little hit and miss so, I advise to over-compensate almost to the point at which the circuit becomes too sluggish in responding. I don't think this will be an issue of course. @paulplusx \$\endgroup\$ – Andy aka Feb 15 at 11:56
  • 1
    \$\begingroup\$ To a large extent all op-amps have a problem when driving capacitance. For instance you may be able to just about drive (say) 100 pF and, to make this situation improved, if you add feedback capacitance it might get worse in terms of instability or oscillation but, if you keep on adding capacitance, eventually you'll "reach the other side" and things will stabilize. I did write a good answer on this so I'll try and locate it. \$\endgroup\$ – Andy aka Feb 15 at 12:10
  • 1
    \$\begingroup\$ electronics.stackexchange.com/questions/493699/… - try reading this @paulplusx \$\endgroup\$ – Andy aka Feb 15 at 12:13
3
\$\begingroup\$

If your concerned about parasitics then put them in the model. Simulate the worst case parasitics.

A 12mil 1 inch trace has 35mΩ's of resistance and roughly ~12nH and 1.5pF.

Connectors can have resistances in the 100mΩ's range.

Most of the traces between components will be much shorter than this, but put in a 35mΩ resistor between various components and measure the error in the spice simulation. If it is a problem then keep the trace length smaller.

There are voltage offsets in the opamps, find the voltage offset in the datasheet and put in the worst case Vos by inserting a voltage source with the same max Vos in the datasheet between one of the terminals and the signal of the op amp.

Make sure the leakage of the analog switch won't be a problem.

I once built a system to measure resistance, my range was smaller, but I used a changeable current source connected to a DAC and and ADC to measure the voltage across a sense resistor. With a 24bit ADC I was able to measure the resistance to within ~4mΩ on a 1k resistor.

\$\endgroup\$
0

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.