I am currently designing the address decoder of a piece of ReRAM that will be sent to TSMC and manufactured. I have studied in class and textbook that there are two common address decoder designs. One uses CMOS AND gate with a set of predecoders to speed up the circuit.
The other one uses dynamic NOR gates with N NMOS transistors in parallel, where N is the number of address lines to be decoded. I am wondering what is the design that the industry (etc. big companies like Samsung and Intel) is currently using?
If the industry is using the former one, do they split the entire decoder into smaller ones such as 3 to 8 decoders?
Cause a single memory can have tens of thousands of word lines and building a 10 to 1024 decoder using only two-input AND gates seems improbable to me. Thanks!