I am currently designing the address decoder of a piece of ReRAM that will be sent to TSMC and manufactured. I have studied in class and textbook that there are two common address decoder designs. One uses CMOS AND gate with a set of predecoders to speed up the circuit.

The other one uses dynamic NOR gates with N NMOS transistors in parallel, where N is the number of address lines to be decoded. I am wondering what is the design that the industry (etc. big companies like Samsung and Intel) is currently using?

If the industry is using the former one, do they split the entire decoder into smaller ones such as 3 to 8 decoders?

Cause a single memory can have tens of thousands of word lines and building a 10 to 1024 decoder using only two-input AND gates seems improbable to me. Thanks!

  • \$\begingroup\$ I always thought the process went something like this: You code it up in an HDL, simulate it and then find out if it meets the constraints. There is a tradeoff between speed and real estate because faster circuits require more logic \$\endgroup\$
    – Voltage Spike
    Feb 9, 2021 at 20:14
  • 1
    \$\begingroup\$ This is interesting. I didn't think of using HDL initially. But then what kind of design does the HDL transform to? What controls this process (e.g. what decides which kind of design to use)? \$\endgroup\$
    – Jeffrey Yu
    Feb 9, 2021 at 20:53
  • 1
    \$\begingroup\$ @VoltageSpike For things like memory address decoders the design process is much different. The layout is hand-drawn to pitch match the memory row height and the routing of the address lines is carefully optimized. It's not HDL design. \$\endgroup\$ Feb 9, 2021 at 20:54

1 Answer 1


In my experience the dynamic NOR structure is most commonly used, because the individual decoders are very small and will match the height of the memory rows. This requires that both the true and complement version of the address bits is routed through the decoders (usually orthogonal to the direction of the word line) and then each of the NMOS transistor gates is tied to either the true or complement version of one address bit. While the simplest version of this is dynamic, you can also add a weak feedback path to make it static.

  • \$\begingroup\$ Thanks for answering my question! If the layout is hand-drawn to match the row height, is the circuit also manually built or synthesized from Verilog code? I am building a 10 to 1024 decoder and it requires a huge amount of effort to build and test in Cadence Virtuoso. So I am wondering if I am heading in the right direction. \$\endgroup\$
    – Jeffrey Yu
    Feb 17, 2021 at 9:16
  • \$\begingroup\$ In my experience, the geometry of all of the parts of a memory array is carefully designed so that the pieces fit together like a jigsaw puzzle. The physical design is not synthesized from HDL, it is hand drawn. You could synthesize the decoders but they will probably be larger and slower. Whether that is the "right direction" for your project is something only you can answer. \$\endgroup\$ Feb 17, 2021 at 12:39

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.