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When I try to simulate a circuit I designed in Proteus, I'm getting an unexpected output from the op-amp.

As you can see from the image, for op-amp U1:A, the inverting terminal voltage is about 3.25V while the non-inverting terminal voltage is set to 2.5V reference.

Hence as the inverting terminal voltage is greater than the non-inverting terminal voltage, the output should be -VSat i.e. 0V.

However, I'm getting 3.72V as output.

Can you guys please tell me where I've made my mistake? The op-amp is an LM324 as a single rail op-amp. ( +Vsat = 5V, -Vsat = 0V.)

The expected inputs for JK F/F are 0 1. Which means output of U1:A should be 0V and U1:C should be 5V (Logic 1.)

Reference Image:

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  • \$\begingroup\$ LS TTL requires a couple of milliamps to pull the input low. R16 won’t let that happen. \$\endgroup\$
    – Kartman
    Feb 10 at 7:47
  • \$\begingroup\$ Can you suggest any modification in the current circuit. What value of resistor should be used ? \$\endgroup\$
    – Mihir
    Feb 12 at 6:15
  • \$\begingroup\$ For your own education, I suggest you read the datasheet for the 74ls08 and find the spec for input low current. You can then apply Ohm's law to solve for resistance. Or chose a 74HC08 and avoid the issue. \$\endgroup\$
    – Kartman
    Feb 12 at 9:45
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Can you guys please tell me where I've made my mistake? The op-amp is an LM324 as a single rail op-amp.

You are measuring AC volts not DC volts: -

enter image description here

This means that your analysis is invalid.

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