When I try to simulate a circuit I designed in Proteus, I'm getting an unexpected output from the op-amp.
As you can see from the image, for op-amp U1:A, the inverting terminal voltage is about 3.25V while the non-inverting terminal voltage is set to 2.5V reference.
Hence as the inverting terminal voltage is greater than the non-inverting terminal voltage, the output should be -VSat i.e. 0V.
However, I'm getting 3.72V as output.
Can you guys please tell me where I've made my mistake? The op-amp is an LM324 as a single rail op-amp. ( +Vsat = 5V, -Vsat = 0V.)
The expected inputs for JK F/F are 0 1. Which means output of U1:A should be 0V and U1:C should be 5V (Logic 1.)