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In a book about computers I have this transistor diagram:

enter image description here

the first two transistors are p types and the second two are n types. I am wondering how it should have been drawn if we close the circuits, because as far as I know we must ahve closed curicuits to get electricity.

1. The first idea I have is that we must close the the ground with the power supply, is this correct? This part would look like this? Notice the top here, I have drawn the red line above the horisontal line, but maybe it should be just below the horistontal line?

enter image description here

  1. Secondly they talk about C beeing connected to ground or 1,2 Volts, does that mean that we close the curicuit C like this:? enter image description here

  2. Now I must draw the line in the subtrate in the transistors, here I have two options. I only draw one p transistor and one n transistor. Option 3a)

enter image description here

Or 3b:

enter image description here Are wither 3a oe 3b correct?

And maybe they would be short-curcuited if I draw it like I did, so maybe I should have added some resistors aswell? If the drawing are wrong, could you please explain how we would draw the full circuit?

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  • \$\begingroup\$ because as far as I know we must ahve closed curicuits to get electricity. No, a closed circuit is needed to make a current flow. In your attempt to "close the circuits" you're overconfusing yourself as these CMOS logic circuits have the property that no current flows. The current only flows for a very short time when the circuit changes state. At that moment the power supply is "shorted" but since these MOSFETs are always quite small, only a very small current flows so the shorting is not an issue. \$\endgroup\$ Feb 10, 2021 at 12:45

4 Answers 4

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  1. Your first picture is almost correct, but you can't connect the top and ground parts directly. If you would connect them you would build a short circuit and you had no voltage over your transistor circuit anymore.
    The way the diagram in the book is drawn is a typical way to show where the (+) and the (-) of the voltage source is connected. I have drawn a battery (red) in the circuit to show what exactly that means. At the top you have the positive voltage of say 1.2V and the ground symbols are connected to the negative terminal and are interpreted as 0V.

  2. C is not connected to 1.2V or ground at the output (like you have drawn it), but by the transistors. That's the whole purpose of this circuit. C is the output that (dependent on the input signals) is either connected by the upper two transistors to the positive terminal (1.2V) or the negative terminal (0V). I have drawn these two paths in blue and green.
    This way the circuit fulfills the role as a logic gate: The two inputs A and B both have to be at LOW potential for the upper two transistors to be conductive. So with both inputs LOW, the output C is connected to logic HIGH (the supply voltage). The lower two transistors are not conductive in this case. But if one of the inputs is at HIGH potential, one of the two upper transistors does not conduct anymore, so the output is not connected to the supply. Instead one of the lower transistors gets conducting and the outputs is "pulled LOW".
    The circuit is representing a NOR gate.

enter image description here

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  • \$\begingroup\$ Thank you, I just have two questions. Does the blue line tell us that the substrate of the p transistors are connected to the power supply and C, and does the green lines thell us that the substrate of the n transistors are connected to ground and C? \$\endgroup\$
    – user394334
    Feb 11, 2021 at 1:04
  • \$\begingroup\$ No, the green and blue lines tell us nothing about the substrate, I justed drew them to show the current paths in the two different possible states of the circuit. \$\endgroup\$
    – jusaca
    Feb 11, 2021 at 6:58
  • \$\begingroup\$ The substrate basically is connected to that transistor terminal, that the gate voltage is referenced to. The substrate of n-channel transistors is typically connected to ground and the substrate of p channel transistors to the supply voltage. \$\endgroup\$
    – jusaca
    Feb 11, 2021 at 6:58
  • \$\begingroup\$ Thank you, just one last question:Do we not need to close the circuit after C?, or is it not meant to flow electricity through C? Should C also be connected to the red line? \$\endgroup\$
    – user394334
    Feb 13, 2021 at 2:15
  • \$\begingroup\$ No, don't connect C to the red line! You would short circuit your output. The output C is used to connect the signal voltage of this NOR gate to some further logic gates, to a microcontroller, or whatever uses this signal. The output is not meant to drive significant current, you want to measure the output voltage with an impedance as high as possible. \$\endgroup\$
    – jusaca
    Feb 13, 2021 at 11:40
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To make the circuit complete, first add an ideal voltage source for each of the inputs (A and B). The positive end of the voltage source connects to the input signal and the negative end connects to ground. These sources represent the logic input signals, and may have values of 1.2V or 0V.

Another ideal voltage source is the power supply. Its positive end connects to the horizontal bar at the very top and its negative end connects to ground. It has a value of 1.2V

All of the PMOS substrates are connected to the positive end of the power supply voltage. All of the NMOS substrates are connected to ground. This is not strictly required but it is the most common situation for logic circuits.

All of the signals described as "ground" are connected together. You can draw an actual wire to do this but generally we connect them to a special ground symbol, such as triangle in your diagram, and understand that these symbols are actually connected together.

All of the additional components and connections I described have been intentionally omitted from your schematic, because most readers will understand that they are implied and the drawing would just be cluttered if they are all drawn out.

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  • \$\begingroup\$ This looks like an equivalent drawing for a MOS gate. Vss on top, Vdd on the bottom. \$\endgroup\$
    – Gil
    Feb 10, 2021 at 20:28
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The "bubble" on the PMOS device gates, indicate that these are "active-low" inputs. With A and B low, the top two PMOS are "on", meaning that there is a direct connection between their drain and source (top and bottom) terminals. Since one end of this series connects to the supply voltage, and the other end to output C, A and B being low makes C high because it is connected.

Likewise, the bottom two NMOS devices do not have a bubble on their gate, indicating that they are "active high" devices. When A and/or B are high, either or both of these are on, connecting output C to ground.

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schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. Consider the CMOS transistors as simple pairs of complimentary switches.

In all cases except one the output is pulled low by the ground-side switches. These effectively connect the output to ground and will sink any current provided by the load.

In the first case when both inputs are on the ground is disconnected and the output is connected to positive supply. The output goes high and will source any current demanded by the load.

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