# Why are the voltages the way they are in this transistor circuit?

This question is about what my book calls "transmission voltage" when an nmos is conncted to the power source, or a pmos is connected to ground. It has a hypothetical diagram ass shown:

It also has a text to describe this, I have underscored in red the most relevant part:

1. In the first case when we have 0 volts in A and 0 volts in B. Do we then get 1 volts because there is 0,5 volts over each of the p-types? If so, what is the details that gives us this voltage over the p types?

2. Do we in the other cases get 0,7 volts, because we are connected to the power supply, but we lose 0,5 volts over the n type? Again, what is the details that causes a (negative) voltage over the n types in this case?

• These hypothetical gates may not have enough gate voltage to conduct, so there is some conduction voltage for ON and OFF . This is hypothetical (not real). But it is not an OR gate but rather a NAND gate. Commented Feb 11, 2021 at 1:51
• right ... the Nmos Pmos are reversed Commented Feb 11, 2021 at 2:14
• here's a rough simulation using Vt=0.7 gates tinyurl.com/y48r7c55 OR gates with poor margins Commented Feb 11, 2021 at 2:21
• The problem is Pch gates don't work well on the low side as well as the NAND gate with Pch on the high side tinyurl.com/y26yvjct Commented Feb 11, 2021 at 2:24
• Are you familiar with analog MOS amplifiers? If so, what can you conclude about your FETs when they're configured in a common drain topology? Commented Feb 11, 2021 at 2:47

Basically it comes down to how logic-level FETs need to be biased to be fully on or off.

FETs have a characteristic gate-source threshold voltage, Vgs, that must be met before they turn on.

• N type: the gate voltage must be above the source +Vgs threshold
• P type: the gate voltage must be below the source -Vgs threshold

Let's have a look in a sim with what they drew, and compare it to the behavior when N and P are in their 'right' places:

Simulate it here: NAND Gate Sim

The example they show never gives the FETs a fighting change to do their jobs, because the Vgs biasing isn't right. Basically, the Fig. 3.7(a) circuit makes the FETs behave as followers, which means that the source will always be no closer than one Vgs threshold to the gate voltage.

That is, assuming Vgs threshold of 0.7V (as in the sim):

• N-FET with source at +1.2, with Gate at +1.2, Drain will never be higher than 0.7V (1.2V - 0.7V);
• P-PET with source at 0V, with gate at 0V, Drain will never be lower than 0.7V (0V - (-0.7V))

The sim doesn't show exactly those values. Why? The influence of the two low-side FETs in series, and the exact FET model the sim used.

The point is, the FET needs to have Vgs biased to a useful value to get the result you desire. The second diagram swaps the P and N FETs and voila! gives a functioning NAND gate.

• Thank you very much, but I have some follow up questions.1.Do you mean that 1,2V-0,7 V=0,5 V, not 0,7 V?(the third bullet point).2.It seems in the simulation that we get the opposite values than in the drawing, that is when we have to L, we have 0,7V, but in the other cases we are closer to 1V, it should be opposite?3. COuld you please explain in all 4 cases why the output is the way it is with the input on A and B as it is.4.Does follower just mean that the threshold voltage is not enough so that means that the souce voltage will be the gate voltage minus the threshold voltage? Commented Feb 14, 2021 at 12:00
• The changes in the voltage is due to the series pair being biased near Vgs, in ‘transmission gate’ threshold. That’s what the text is trying to explain. Try changing the Vgs threshold in the sim and see how it influences the output value. Look at what the biases are doing vs. Vgs, and especially, how that series pair interacts. Commented Feb 14, 2021 at 19:30
• At the same time, the ‘transmission gate’ business is a bit confusing. The near-Vgs biasing mode is used for making a voltage follower or for translating voltage. It’s not useful for making a gate like this, which relies on using saturated mode (that is, Vgs well above threshold.) Commented Feb 14, 2021 at 19:35
• But why does the simulation show opposite values as opposed to what is in the table in my first post? It shows 0,7 when A and B is 0 and higher in the other cases, that is opposite of what is in the table. Commented Feb 14, 2021 at 22:45
• The table is a hot mess that doesn’t match anything. The actual result will vary based upon the FET model in use. Further, the table doesn’t account for the two FETs in series, each with its own bias state. That’s where the simulation comes in, so you can actually see the biasing states. Commented Feb 14, 2021 at 23:00

To understand why the shown arrangement does not work properly, study a similar problem that arises when single NMOS and PMOS are used as transmission gates. In CMOS you have the choice of a detached body, therefore, in theory, the transistor is a totally symmetrical device. So the terminal of the transistor that behaves as the source and drain depends on the direction your trying to pass current through it. This is the key to understand why the circuit you have shown does not work well with the NMOS on top and PMOS on the bottom.

In the circuit shown, the source of both the PMOS and NMOS will be the output node. Now this should immediately give off some red flags as you want that node to swing from 0 to VDD, meaning that the VGS of both transistors will change considerably when the output changes! What this means is, before the output changes fully from one end of the rail to the other, the transistor will switch off before that happens fully, leaving the output at some intermediate voltage.

Consider what happens with both inputs are HIGH. The gate of PMOS is at 1.2V and the source of the PMOS, the output node, must be something less than 1.2V, thus the PMOS is off. Now the NMOS gate is also at 1.2V so it tries to turn on, but as this happens the output rises and hence VGS of the NMOS drops, eventually almost switching it off. Thus the NMOS will only operate until the point the output reaches a value such that VGS = Vgate - Vout = VTH = 0.5V. Hence Vout = 1.2 - 0.5 = 0.7V.

Look at the blue trace Reqn. This is the resistance or drive strength of the NMOS driving the output when both inputs are HIGH. Do you see how, because Reqn starts to become huge (in theory infinite) so Vout can only go upto a maximum Vdd-Vth as shown on the x-axis Vout?

• Thank you, but I have one follow up question: It is about this "Now the NMOS gate is also at 1.2V so it tries to turn on, but as this happens the output rises and hence VGS of the NMOS drops, eventually almost switching it off. Thus the NMOS will only operate until the point the output reaches a value such that VGS = Vgate - Vout = VTH = 0.5V. " Why do we have that the output of the nmos rises in this case? Isn't the voltage of the source of the nmos now at zero? And how is the fact that the nmos is connected to ground have anything to do with this? Commented Feb 14, 2021 at 17:09
• Why will the NMOS source be at 0V and who said nmos is connected to ground? ignore the PMOS as it is OFF and imagine just the NMOS with its gate and drain at 1.2V and source (the output node of this cirucit) connected to ground via some large resistance(representing the off PMOS) and some paracitic capacitance. The source will tell begin to rise slowly upto around Vgate - Vth.. Do you see?
– MAM
Commented Feb 14, 2021 at 18:13
• Just ask your self this question: Can a NMOS with drain = 1.2v and gate = 1.2v drive a load connected to its source to 1.2V before switching off? The answer is no, because the NMOS will switch off once the source(output node) reaches 1.2v - Vth, which is what the author is trying to explain. This is what i suspect he means by maximum "transmission voltage".
– MAM
Commented Feb 14, 2021 at 18:18
• So the drain of the nmos is connected to 1,2 volt aswell? And what happens is that the nmos is open, but it will go current through it which will drop the difference of voltage between the gate and the source and that causes the nmos to be turned off? Does the current drop the voltage beacuse there is innter resistane? Commented Feb 14, 2021 at 19:01
• Yes the drain of the NMOS is the top most pin connected to the power rail on the photo you posted. Yes you almost got it, the current through the NMOS starts to flow through the resistance/capacitance at the output node/source node which means slowly this node voltage starts to rise. But as this rises VGS starts to decrease, eventually turning the NMOS off before the source can reach VDD.
– MAM
Commented Feb 14, 2021 at 19:37