# 4 layer stackup, inner layers GND & PWR

To "somewhat" quote Rick Hartley, "the energy isn't in the traces & planes but in between", I'm now wondering, when I use the following stackup:

1. Sig
2. GND
3. PWR
4. Sig

You would have energy between layer 4 and 2 in case of a 'HIGH' signal on layer 4 right? So that means the distance between current and return current become larger than needed. Isn't it better then to use the following stackup:

1. Sig/PWR
2. GND
3. GND
4. Sig/PWR

Asking this because I see a lot of PCB's being designed in the first stackup topology. In addition i have another question. Somebody told me I could also make a mix in layer 3 of GND and PWR. I wonder, is this a good idea, to mix different potentials on one plane? why or why not? If you were to use this method of mixing GND and PWR in layer 3, how would you do this? adding only PWR polygons under IC's, or definately not?

## 2 Answers

It's really a lot more complicated than that. Usually you can do two kind of 4 layer stackup:

1. Signal
2. Gnd
3. Power
4. Signal

Which is the common one and

1. Power
2. Signal
3. Signal
4. Gnd

Which is another one for special occasions.

You could do

1. Signal
2. Gnd
3. Signal
4. Power

But I've never seen it around (probably for practical reasons). Also remember that, from a fabrication view, you can do a 4 layer with either one core and two prepregs or two cores and one prepreg. For cost reasons it's almost done in the first way and that's influences the copper weight availability for the different layers and the manufacturability of precision alignments.

For simplicity, just consider only the case where all the layers have the same copper weight. However, remember that usually cores are thicker than prepregs, and that influences controlled impedence lines, too!

It is right that, in high speed/RF layouts, you need to design with a return plane in mind (the 'energy in beetween' is more a wave propagation thing, but is relevant). So the best way is to have a signal plane adjacent to its own return (i.e. the ground plane).

But keep in mind that power planes are usually heavily bypassed to ground so, in a pitch, they could do as auxiliary reference plane. Just don't trust them for controlled impedance.

The first stackup is AFAIK the more common. Top signal layer is in an almost ideal situation, regarding grounding. Bottom signal is not since is the farthest from the ground layer but at least it has the power plane in the middle to help.

The second stackup from a grounding and EMC point is the best one. Signal lines are shielded by the ground planes, and, although they are adjacent, are usually separated by the core which is thicker.

It could be argued that the third layout should be the best for ground referencing but I have no experience with that and there no literature on that layout. There must be reasons.

Why then is the first one the most popular? Well, most component are SMD and they need to be mounted on the top or bottom side. So if the signal lines are on the middle planes you need to add a via to each single pad. Not only, the component themselves make holes in the plane, which is the worst since it's not a plane anymore. I've only seen this layout in RF designs since it allows you to make real microstrips (signal 'sandwitched' between ground).

As most things in engineering is a tradeoff, you need to consider the environment and the required performance of the circuit to decide.

EDIT: Regarding your signal/power proposal… it's not bad in itself but power planes need to be at very low impedence. So if you add signals you cut them and they lose this property.

However this is quite frequent in 6 and 8 stackups where you maybe have a power plane for some area (like a Vcore for an FPGA) but you can use it as a signal layer for other section where that kind of power is not remotely useful. Look at the reference design for the big NXP iMX RT controllers (or other big logic devices), it's quite enlightening

If your decoupling is good then there's little difference in principle between using a ground plane and using a power plane for screening. In a typical stack you'll have the top two layers close together, a relatively large gap in between and then the bottom two layers close together, so placing a ground/power planes on the internal layers will be effective. For SMT it's wise to track signals on the component side in preference, to minimise the number of vias. Using a split plane (power and ground on the same layer) is quite possible, but it necessarily fragments the planes and so makes them less effective. Apart from that, there's no problem mixing potentials on the same layer.

• One gotcha I would like to add to @frog's fine answer about split power/gnd planes in same layer is when signals are crossing over the gaps. This will give signal disruption on fast edges because of the mirror current being deviated in the power/gnd plane. Think of it as being similar to had you put an inductor in series with your signal. The best you can do is add decoupling caps close by the crossing so the mirror current only has to travel a short distance. Equivalent to minimizing the mentioned inductor value. Feb 12, 2021 at 10:30
• Great answer @Frog, but one thing that remains is that when you would use a PWR plane only at layer 3, you would have the energy between the return path at layer 2 and the currents at layer 4 to be placed in between at layer 3? Could this not give issues?
– Mart
Feb 12, 2021 at 10:40
• Yes, theorically it could give issue. However the power plane at layer 3 is low impedance and hard to disturb and itself is relatively quiet (no concentrated current). In RF or high precision analog you can actually use a section of the power plane as ground effectively creating a guarded trace or even a microstrip. Feb 12, 2021 at 16:56
• All valid comments. Vias have a certain amount of inductance, and the copper plating is typically thinner than the amount on the copper layers themselves, so effective use of an internal power or ground plane requires the use of relatively large or numerous vias and decoupling capacitors on the same side as the loads. I’ve seen BGA designs with decaps on the back, but this is in my view the least-bad option, where escaping the signal tracks on the top layer is impossible.
– Frog
Feb 12, 2021 at 19:23