It's really a lot more complicated than that. Usually you can do two kind of 4 layer stackup:
- Signal
- Gnd
- Power
- Signal
Which is the common one and
- Power
- Signal
- Signal
- Gnd
Which is another one for special occasions.
You could do
- Signal
- Gnd
- Signal
- Power
But I've never seen it around (probably for practical reasons). Also remember that, from a fabrication view, you can do a 4 layer with either one core and two prepregs or two cores and one prepreg. For cost reasons it's almost done in the first way and that's influences the copper weight availability for the different layers and the manufacturability of precision alignments.
For simplicity, just consider only the case where all the layers have the same copper weight. However, remember that usually cores are thicker than prepregs, and that influences controlled impedence lines, too!
It is right that, in high speed/RF layouts, you need to design with a return plane in mind (the 'energy in beetween' is more a wave propagation thing, but is relevant). So the best way is to have a signal plane adjacent to its own return (i.e. the ground plane).
But keep in mind that power planes are usually heavily bypassed to ground so, in a pitch, they could do as auxiliary reference plane. Just don't trust them for controlled impedance.
The first stackup is AFAIK the more common. Top signal layer is in an almost ideal situation, regarding grounding. Bottom signal is not since is the farthest from the ground layer but at least it has the power plane in the middle to help.
The second stackup from a grounding and EMC point is the best one. Signal lines are shielded by the ground planes, and, although they are adjacent, are usually separated by the core which is thicker.
It could be argued that the third layout should be the best for ground referencing but I have no experience with that and there no literature on that layout. There must be reasons.
Why then is the first one the most popular? Well, most component are SMD and they need to be mounted on the top or bottom side. So if the signal lines are on the middle planes you need to add a via to each single pad. Not only, the component themselves make holes in the plane, which is the worst since it's not a plane anymore. I've only seen this layout in RF designs since it allows you to make real microstrips (signal 'sandwitched' between ground).
As most things in engineering is a tradeoff, you need to consider the environment and the required performance of the circuit to decide.
EDIT: Regarding your signal/power proposal… it's not bad in itself but power planes need to be at very low impedence. So if you add signals you cut them and they lose this property.
However this is quite frequent in 6 and 8 stackups where you maybe have a power plane for some area (like a Vcore for an FPGA) but you can use it as a signal layer for other section where that kind of power is not remotely useful. Look at the reference design for the big NXP iMX RT controllers (or other big logic devices), it's quite enlightening