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In structural VHDL, is it acceptable to use signals declared with the same name in different components?
For example:
Component_1 uses a signal declared Temp_1
Component_2 also uses a signal declared Temp_1
These two components are both instantiated in the same higher top level source code?
Signal names are isolated within VHDL modules. So there is no "connection" between same-named signals between modules. So it's perfectly acceptable to use the name "Temp_1" in different modules. The only way to connect is via ports.
