I'm working on a high-speed data collection device for an ADC running at 80 Msps. After digging through resources on MCUs and asking several questions here and in other forums, I've turned my attention to FPGAs. From what I understand, an FPGA-based circuit would be the fastest method to collect data from a series of inputs and store that data. The event I'm trying to capture will be relatively short and can be set up with a trigger, so I'm thinking of sending data to SDRAM during the event and extracting it later via USB or some other interface. The ADC I'm using is the MAX1448, which provides a 10-bit parallel output with each clock cycle at 80 MHz (with a pipeline delay of ~5.5 cycles).
When looking at MCUs, I gathered that for each input pin, instruction cycles were needed to send that bit from the GPIO to DMA or other peripherals. So just to execute one instruction for each bit, I needed a clock speed at least 10x my ADC sample rate. From what I understand, FPGAs get around this bottleneck by programming the data path beforehand. My question though, is what should I be looking for in a FPGA in order to store ADC data at a specified rate with a set number of bits/inputs? How does the clock speed of a FPGA determine the data transfer rate, or what clock speed do I need to look for to achieve 800 Mbps (or 10 data paths at 80 Mbps each)?