Today, I came across this problem on QuickSilicon's RTL Hackathon. It was to design an Endian converter.
The requirements were
- The output should be available in the same cycle
- The module should produce an output every cycle.
- All flip-flops, if any, should be triggered on the rising edge of the clock and resets should be asynchronous.
The only way this would work (i.e output is provided on the same cycle as the input is seen) if there are no flip-flops in the module.
module big_endian_converter #( parameter DATA_W = 32 )( input wire clk, input wire reset, input wire [DATA_W-1:0] le_data_i, output wire [DATA_W-1:0] be_data_o ); // Write your logic here logic [DATA_W-1:0] be_data; always_comb begin // convert endian end assign be_data_o = /* code for reset */; endmodule
That would imply that the design is combinational and the clock signal is not really used. Is this possible for a signal in the module is not used? Can this unused signal still be useful? If yes, how can it be useful?
Is it common to include a clock input for non-sequential logic?