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When creating components in VHDL and instantiating them in a source file, does it matter if component have outputs that have the same name.

For example component A has an output called Out_1 and component B has an output also called Out_1. They are nested in source files in a way that when I instantiate components A and B, I am assigning output values Out_1 => Out_1.

Now when I simulate in a test bench, the signals are orange and uninitialized. Is this something that should be avoided?

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  • \$\begingroup\$ You can instantiate two components each with an OUT1 port. In their port maps, simply map the two OUT1 ports to two different signals (unless you want to short their outputs together) \$\endgroup\$
    – user16324
    Commented Feb 13, 2021 at 21:47
  • \$\begingroup\$ IEEE Std 1076-2008 12.1 Declarative region. A component declaration is a declarative region. 12.3 Visibility "A declaration is said to be hidden within (part of) an inner declarative region if the inner region contains a homograph of this declaration; the outer declaration is then hidden within the immediate scope of the inner homograph." They're in different declarative regions. 12.3 tells the ports are also visible in their respective component instantiations as formals in association lists. The two OUT_1 ports are distinct and don't exist in the same name space. \$\endgroup\$
    – user8352
    Commented Feb 13, 2021 at 23:09

1 Answer 1

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When creating components in VHDL and instantiating them in a source file, does it matter if component have outputs that have the same name.

For example component A has an output called Out_1 and component B has an output also called Out_1. They are nested in source files in a way that when I instantiate components A and B, I am assigning output values Out_1 => Out_1.

No problems, but it should be different than the port name so it doesn't get confusing. There is a distinction between signals names and port names.

The port names must be the same though for each instance of the same component (obviously).

If you try to assign the same signal to two output ports you will get a multi-drive error.

Now when I simulate in a test bench, the signals are orange and uninitialized. Is this something that should be avoided?

It's a good idea to initialize but I think sometimes you can get away with not initializing intermediary signals since they get affected by initialized signals further upstream.

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