# LDR, LDRD and STR instructions with immediate offset in ARM Cortex-M3

The Cortex™-M3 Devices Generic User Guide explains the instruction LDRD R8, R9, [R3, #0x20] as "Load R8 from a word 8 bytes above the address in R3, and load R9 from a word 9 bytes above the address in R3". I would like to ask why 0x20 equals to 8 bytes and not 32 bytes?

The guide explains the instruction LDRNE R2, [R5, #960]! as "Loads (conditionally) R2 from a word 960 bytes above the address in R5, and increments R5 by 960". Is the value or the address of R2 updated? Is the value or address of R5 incremented?

The guide explains the instruction STRH R3, [R4], #4 as "Store R3 as halfword data into address in R4, then increment R4 by 4". Is the value or address of R4 incremented?

• focus on the architectural reference manual for these details, it is all described there. The TRMs are good, arms other documents I have found lacking or confusing and in this case has typos Feb 14, 2021 at 19:28
• 8 and 9 words not bytes, a typo Feb 14, 2021 at 19:28
• I think they have one called a programmers guide, something with the word programmer in the name, avoid that one. Feb 14, 2021 at 19:29
• @jwh20 Thank you for your useful answer. I would like to ask whether STRH R3,[R4] is equivalent to MOV R4, R3. STRH R3, [R4] stores the value of register R3 into the address specified by R4, which is the same as copying the value of R3 into R4. Is that correct?
– user276722
Feb 18, 2021 at 2:15

LDRD R8, R9, [R3, #0x20]

I believe that is a mistake in the document. This instruction loads #0x20 (i.e. 32 bytes) above the address in R3 as you would expect.

LDRNE R2, [R5, #960]!

In this case the VALUE of R5 is incremented by the specified immediate value, 960. If you consider that an address, then it's an address. In most cases this will be an address.

STRH R3, [R4], #4

Again, as with the previous instruction, the VALUE in R4 is incremented, by 4 in this case. If you, the programmer, are considering this to be an address, then it's an incremented address.

In the 2nd two cases only the register is modified. Any memory address pointed to by these is unaffected.

BTW, a really handy thing to help your ARM Assembly learning is one of the many ARM emulators. I like this one:

ARM Emulator

• I will second the recommendation for cpulator to try ARM assembly. However, I don't think you can specify a Cortex-M3 target. I have only succeeded in simulating a Cortex-A9 with full 32-bit ARM instructions. Feb 14, 2021 at 15:35
• @ElliotAlderson Yes I believe you are correct, that specific emulator doesn't directly support the M3. The good news is that for many cases the specific ARM processor doesn't matter. I believe this is one of those cases. Feb 14, 2021 at 16:15