# JK Flip-Flop Counter: How to reset a counter?

I currently have a 3-bit asyncronous counter (built using J-K flip flops) that continuously counts up. However, I am struggling to figure out how to reset the counter to 0 when an input (Reset) is true.

According to the J-K flip-flop truth table, when J = 0 and K = 1, Q = 0. Thus, I feed the clock signal into the K inputs of the flip-flop generating the least significant bit but I feed into the J input the opposite of the Reset input (chaining a NOT gate to it). Below is my asyncronous 3-bit counter:

However, when Reset is activated, the counter freezes instead of being reset to 0. This seems strange, considering that I am following the boolean algebraic properties of the J-K flip-flop.

• Why not use the reset input? Feb 14, 2021 at 13:52

The trivial solution is to just tie RESET to the reset pin of all the flip flops.

The more interesting case is when you need a synchronous reset, i.e. RESET changes on clock edge and you want all flip flops to reset on a clock edge.

A J-K flip flop will count (toggle) when both J and K = 1. We can make a free-running counter by just using J, tying K high.

To reset Q in a J-K flip flop we must set J=0 and K=1. If we make RESET active low, then the circuit below does that.

When RESET is low, all J inputs are forced low, and since all K are high, on next clock edge all Q outputs will reset to 0.

When RESET is high, the AND gates will pass on their input unchanged and the circuit functions as if the AND gates aren’t there, i.e. becomes the top circuit.

You are doing a ripple counter with synchronous logic. Adding a reset doesn't really work very well. I assume you want to do a synchronous reset, an asynchronous reset with regular J-Ks (i.e. without asynch inputs) is a mess.

You really want a synchronous counter, it's way easier to design and doesn't suffer from the timing issues of a ripple counter. Also it's the form you'll normally do logic these days.

Just do a better state transition table and rebuild your combinatorial network.

For example, a 2 bit counter would usually be

State CNT_EN    Next State
0      H        1
1      H        2
2      H        3
3      H        0
x      L        x


This is a bare 2 bit counter with enable: if the enable is true the counter advances. Two flops for building it. If the counter will be counting for every clock cycle the enable can be omitted.

The same counter with synchronous reset would be:

State CNT_EN Reset   Next State
0      H     L       1
1      H     L       2
2      H     L       3
3      H     L       0
x      L     L       x
x      x     H       0


In this way when the reset input is asserted a transition is forced to state 0. Also notice, no more states are needed, it's only a more complex combinatorial network

Does your model consider setup and hold times? If so, using Received_Input as input for the clock and K of the LSB might cause setup violations.

Anyway... considering your logic if J of the LSB is zero for a reset, b_0 will become zero with the next rising edge of Received_Input (assuming there are no setup violations) and will remain zero as long as Reset is zero. J and K of the second flip flop are zero, when b_0 is zero. This leads to b_1 not changing. And so on for the third stage.

If you want a proper reset, you need a logic which sets J to zero and K to one in each stage. E.g. an OR with Reset before each K and an AND with NOT Reset before each J.